參數(shù)資料
型號(hào)： ADSP-21992YST
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： Mixed Signal DSP Controller With CAN
中文描述： 16-BIT, 100 MHz, OTHER DSP, PQFP176
封裝： LQFP-176
文件頁(yè)數(shù)： 10/49頁(yè)
文件大?。?/td> 602K
代理商： ADSP-21992YST
For current information contact Analog Devices at (781) 937-1799
ADSP-21992
Separate auxiliary PWM synchronization signal and asso-
ciated interrupt (can be used to trigger ADC Convert
Start).
Separate Auxiliary PWM shutdown signal (AUXTRIP).
The ADSP-21992 integrates a two channel, 16-bit,
auxiliary PWM output unit that can be programmed with
variable frequency, variable duty cycle values and may
operate in two different modes, independent mode or offset
mode. In independent mode, the two auxiliary PWM gen-
erators are completely independent and separate switching
frequencies and duty cycles may be programmed for each
auxiliary PWM output. In offset mode the switching
frequency of the two signals on the AUX0 and AUX1 pins
is identical. Bit 4 of the AUXCTRL register places the
auxiliary PWM channel pair in independent or offset mode
The Auxiliary PWM Generation unit provides two chip
output pins, AUX0 and AUX1 (on which the switching
signals appear) and one chip input pin, AUXTRIP, which
can be used to shutdown the switching signals, for example
in a fault condition.
August 2002
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
10
REV. PrA
PRELIMINARY TECHNICAL DATA
Encoder Interface Unit
The ADSP-21992 incorporates a powerful encoder
interface block to incremental shaft encoders that are often
used for position feedback in high performance motion
control systems.
Quadrature rates to 53 MHz (at 80 MHz peripheral
clock).
Programmable filtering of all encoder input signals
32-bit encoder counter
Variety of hardware and software reset modes
Two registration inputs to latch EIU count value with
corresponding registration interrupt
Status of A/B signals latched with reading of EIU count
value.
Alternative frequency & direction mode
Single north marker mode
Count error monitor function with dedicated error
interrupt
Dedicated 16-bit loop timer with dedicated interrupt
Companion encoder event (1
T) timer unit.
The encoder interface unit (EIU) includes a 32-bit quadra-
ture up/down counter, programmable input noise filtering
of the encoder input signals and the zero markers, and has
four dedicated chip pins. The quadrature encoder signals
are applied at the EIA and EIB pins. Alternatively, a
frequency and direction set of inputs may be applied to the
EIA and EIB pins. In addition, two north marker/strobe
inputs are provided on pins EIZ and EIS. These inputs may
be used to latch the contents of the encoder quadrature
counter into dedicated registers, EIZLATCH and
EISLATCH, on the occurrence of external events at the EIZ
and EIS pins. These events may be programmed to be either
rising edge only (latch event) or rising edge if the encoder is
moving in the forward direction and falling edge if the
encoder is moving in the reverse direction (software latched
north marker functionality).
The encoder interface unit incorporates programmable
noise filtering on the four encoder inputs to prevent spurious
noise pulses from adversely affecting the operation of the
quadrature counter. The encoder interface unit operates at
a clock frequency equal to the HCLK rate. The encoder
interface unit operates correctly with encoder signals at fre-
quencies of up to 13.25 MHz, corresponding to a maximum
quadrature frequency of 53 MHz (assuming an ideal
quadrature relationship between the input EIA and EIB
signals).
The EIU may be programmed to use the north marker on
EIZ to reset the quadrature encoder in hardware, if
required.
Alternatively, the north marker can be ignored, and the
encoder quadrature counter is reset according to the
contents of a maximum count register, EIUMAXCNT.
There is also a “single north marker” mode available in
which the encoder quadrature counter is reset only on the
first north marker pulse.
The encoder interface unit can also be made to implement
some error checking functions. If an encoder count error is
detected (due to a disconnected encoder line, for example),
a status bit in the EIUSTAT register is set, and an EIU count
error interrupt is generated.
The encoder interface unit of the ADSP-21992 contains a
16-bit loop timer that consists of a timer register, period
register and scale register so that it can be programmed to
time out and reload at appropriate intervals. When this loop
timer times out, an EIU loop timer timeout interrupt is
generated. This interrupt could be used to control the
timing of speed and position control loops in high perfor-
mance drives.
The encoder interface unit also includes a high performance
encoder event timer (EET) block that permits the accurate
timing of successive events of the encoder inputs. The EET
can be programmed to time the duration between up to 255
encoder pulses and can be used to enhance velocity estima-
tion, particularly at low speeds of rotation.
Flag I/O (FIO) Peripheral Unit
The FIO module is a generic parallel I/O interface that
supports sixteen bidirectional multifunction flags or general
purpose digital I/O signals (PF15-PF0).
All sixteen FLAG bits can be individually configured as an
input or output based on the content of the direction (DIR)
register, and can also be used as an interrupt source for one
of two FIO interrupts. When configured as input, the input
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