參數(shù)資料
型號(hào)： ADSP-2192
廠商： Analog Devices, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： DSP Microcomputer
中文描述： DSP微機(jī)
文件頁(yè)數(shù)： 6/40頁(yè)
文件大?。?/td> 1307K
代理商： ADSP-2192
ADSP-2192M
–6–
REV. 0
Interrupt routines can either be nested with higher priority inter-
rupts taking precedence or processed sequentially. Interrupts can
be masked or unmasked with the IMASK register. Individual
interrupt requests are logically ANDed with the bits in IMASK;
the highest priority unmasked interrupt is then selected. The
emulation, power-down, and reset interrupts are nonmaskable
with the IMASK register, but software can use the DIS INT
instruction to mask the power-down interrupt.
The IRPTL register is used to force and clear interrupts. On-chip
stacks preserve the processor status and are automatically main-
tained during interrupt handling. To support interrupt, loop, and
subroutine nesting, the PC stack is 33 levels deep, the loop stack
is eight levels deep, and the status stack is 16 levels deep. To
prevent stack overflow, the PC stack can generate a stack level
interrupt if the PC stack falls below three locations full or rises
above 28 locations full.
The following instructions globally enable or disable interrupt
servicing, regardless of the state of IMASK.
ENA INT;
DIS INT;
At reset, interrupt servicing is disabled.
For quick servicing of interrupts, a secondary set of DAG and
computational registers exist. Switching between the primary
and secondary registers lets programs quickly service interrupts,
while preserving the DSP’s state.
DMA Controller
The ADSP-2192M has a DMA controller that supports
automated data transfers with minimal overhead for the DSP
core. Cycle stealing DMA transfers can occur between the
ADSP-2192M’s internal memory and any of its DMA-capable
peripherals. DMA transfers can also be accomplished between
any of the DMA-capable peripherals. DMA-capable peripherals
include the PCI and AC’97 ports. Each individual DMA-capable
peripheral has a dedicated DMA channel. DMA sequences do
not contend for bus access with the DSP core; instead, DMAs
“steal” cycles to access memory. All DMA transfers use the
Program Memory (PMA/PMD) buses shown in the Functional
Block Diagram
on Page 1
.
External Interfaces
Several different interfaces are supported on the ADSP-2192M.
These include both internal and external interfaces. The three
separate PCI configuration spaces are programmable to set up
the device in various Plug-and-Play configurations.
The ADSP-2192M provides the following types of external inter-
faces: PCI, USB, Sub-ISA, CardBus, AC’97, and serial
EEPROM. The following sections discuss those interfaces.
PCI 2.2 Host Interface
The ADSP-2192M includes a 33 MHz, 32-bit bus master PCI
interface that is compliant with revision 2.2 of the PCI specifica-
tion. This interface supports the high data rates.
USB 1.1 Host Interface
The ADSP-2192M USB interface enables the host system to
configure and attach a single device with multiple interfaces and
various endpoint configurations. The advantages of this design
include:
Programmable descriptors and class-specific command
interpreter.
An on-chip 8052-compatible MCU allows the user to soft
download different configurations and support standard
or class-specific commands.
Total of eight user-defined endpoints provided.
Endpoints can be configured as either BULK, ISO, or
INT, and the endpoints can be grouped and assigned to
any interface.
Sub-ISA Interface
In systems that combine the ADSP-2192M chip with other
devices on a single PCI interface, the ADSP-2192M Sub-ISA
mode is used to provide a simpler interface that bypasses the
ADSP-2192M’s PCI interface. In this mode the Combo Master
assumes all responsibility for interfacing the function to the PCI
bus, including provision of Configuration Space registers for the
ADSP-2192M system as a separate PnP function. In Sub-ISA
Mode the PCI Pins are reconfigured for ISA operation.
CardBus Interface
The CardBus standard provides higher levels of performance
than the 16-bit PC Card standard. For example, 32-bit CardBus
cards are able to take advantage of internal bus speeds that can
be as much as four to six times faster than 16-bit PC Cards. This
design provides for a compact, rugged card that can be completely
inserted within its host computer without any external cabling.
Because CardBus performance attains the same high level as the
host platform’s internal (PCI) system bus, it is an excellent way
to add high speed communications to the notebook form factor.
In addition, CardBus PC Cards operate at a power-saving
3.3 volts, extending battery life in most configurations.
This new 32-bit CardBus technology provides up to 132M bytes
per second of bandwidth. This performance makes CardBus an
ideal vehicle to meet the demands of high throughput communi-
cations such as ADSL.
Table 3. Interrupt Control (ICNTL) Register Bits
Bit
0–3
4
5
6
7
8–9
10
11
12
13–15
Description
Reserved
Interrupt nesting enable
Global interrupt enable
Reserved
MAC biased rounding enable
Reserved
PC stack interrupt enable
Loop stack interrupt enable
Low power idle enable
Reserved
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