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參數(shù)資料
| 型號： | ADSP-2192 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | DSP微機 |
| 文件頁數(shù)： | 34/40頁 |
| 文件大?。?/td> | 1307K |
| 代理商： | ADSP-2192 |
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ADSP-2192M
–34–
REV. 0
Output Drive Currents
Figure 16
shows typical I-V characteristics for the output drivers
of the ADSP-2192M. The curves represent the current drive
capability of the output drivers as a function of output voltage.
Power Dissipation
Total power dissipation has two components, one due to internal
circuitry and one due to the switching of external output drivers.
Internal power dissipation is dependent on the instruction
execution sequence and the data operands involved.
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
Number of output pins that switch during each cycle (O)
The maximum frequency at which they can switch (f)
Their load capacitance (C)
Their voltage swing (V
DD
)
and is calculated by the formula below.
The load capacitance includes the processor’s package capaci-
tance (C
IN
). The switching frequency includes driving the load
high and then back low. Address and data pins can drive high and
low at a maximum rate of 33 MHz.
The P
EXT
equation is calculated for each class of pins that can
drive as shown in
Table 37
.
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation with the
following formula.
Where:
P
EXT
is from
Table 37
P
INT
is I
DDINT
2.5 V, using the calculation I
DDINT
listed
in
Electrical Characteristics on Page 30
.
Note that the conditions causing a worst-case P
EXT
are different
from those causing a worst-case P
INT
. Maximum P
INT
cannot
occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching simultaneously.
Test Conditions
The ADSP-2192M is tested for compliance with all support
industry standard interfaces (PCI, USB, and AC’97). Also, the
DSP is tested for output enable, disable, and pulsewidth. See
Table 35
for the values of these parameters.
Output Disable Time
Output pins are considered to be disabled when they stop driving,
go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by
V is dependent on the capacitive load, C
L
and the
load current, I
L
. This decay time can be approximated by the
equation below.
The output disable time t
DIS
is the difference between t
MEASURED
and t
DECAY
as shown in
Figure 17
. The time t
MEASURED
is the
interval from when the reference signal switches to when the
output voltage decays
V from the measured output high or
output low voltage. The t
DECAY
is calculated with test loads C
L
and
I
L
, and with
V equal to 0.5 V.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start
driving. The output enable time t
ENA
is the interval from when a
reference signal reaches a high or low voltage level to when the
Figure 16. Typical Drive Currents
SOURCE (V
DDEXT
) VOLTAGE – V
0
3.5
0.5
1.0
1.5
2.0
2.5
3.0
4.0
S
D
)
–100
–80
–60
–40
–20
0
20
40
60
V
DDEXT
= 3.3V @
25°C
V
DDEXT
= 5.0V @
25°C
V
OH
V
OL
INPUT CURRENT
OUTPUT CURRENT
80
4.5
5.0
V
DDEXT
= 3.3V @
25°C
V
DDEXT
= 5.0V @
25°C
P
EXT
O
C
×
V
DD
2
×
f
×
=
Table 37. P
EXT
Calculation Example
Pin Type
No. of Pins % Switching
C
f
V
DD
2
10.9 V
10.9 V
10.9 V
10.9 V
= P
EXT
= 0.115 W
= 0.0 W
= 0.003 W
= 0.003 W
P
EXT
=0.04687 W
Address/Data 32
DEVSEL
CBE
CLK
100
0
100
100
10 pF
10 pF
10 pF
10 pF
33 MHz
33 MHz
33 MHz
33 MHz
1
1
1
P
TOTAL
P
=
EXT
P
INT
+
t
DECAY
C
V
I
L
---------------
=
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