參數(shù)資料
型號(hào)： ADSP-2192
廠商： Analog Devices, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： DSP Microcomputer
中文描述： DSP微機(jī)
文件頁(yè)數(shù)： 22/40頁(yè)
文件大?。?/td> 1307K
代理商： ADSP-2192
ADSP-2192M
–22–
REV. 0
In Sub-ISA mode, the ADSP-2192M’s PCI protocol is replaced
with an ISA-like, asynchronous protocol controlled by the strobes
IOR
,
IOW,
and
AEN
. Access is possible only to the PCI Base
Address 4 (BAR4) Registers (the InDirect Access Registers).
The Sub-ISA Address Map is shown in
Table 24
.
An active low
RST
input (to be derived from PCI
RST
and
possible other sources) and an active-high IRQ interrupt output
are available. Power Management is handled by the ADSP-
2192M inputs
PDW1–0
/PME_EN and the ADSP-2192M
output
PMERQ
.
PDW1–0
should be the inversion of the PCI
power state in the function’s PMCSR register.
PDW1
is con-
nected to AD21, and
PDW0
is connected to AD20.
Assertion of
PDW1
low signals a power-down interrupt to the
DSP. Deassertion of
PDW1
high causes a wake-up of the DSP.
The PME_EN output from the Combo Master should reflect the
current PCI function PME_EN bit and should be connected to
the ADSP-2192M AD20 pin. The PMI_EN bit should be set to
enable interrupt and wake-up of the DSP upon any change of the
PME_EN state. If PME_EN is turned off, the DSPs can wake
up if necessary and then power themselves and the ADSP-2192M
completely down (clocks stopped).
PCI Interface to DSP Memory
The PCI interface can directly access the DSP memory space
using DMA transfers. The transactions can be either slave trans-
fers, in which the host initiates the transaction, or master
transfers, in which the ADSP-2192M initiates the PCI transac-
tion. The registers that control PCI DMA transfers are accessible
from both the DSP (on the Peripheral Device Control Bus) and
the PCI Bus.
The PCI/Sub-ISA Bus uses the Peripheral Device Control
Register Space which is distributed throughout the ADSP-
2192M and connected through the Peripheral Device Control
Bus. The PCI bus can access these registers directly.
USB Interface to DSP Memory
The USB interface can directly access the DSP memory space
using DMA transfers to memory locations specified by the USB
endpoints. The registers that control USB endpoint DMA
transfers are accessible from both the DSP (on the Peripheral
Device Control Bus) and the USB Bus.
The Peripheral Device Control Register Space is distributed
throughout the ADSP-2192M and connected through the
Peripheral Device Control Bus. The USB Bus can access these
registers directly.
AC’97 Codec Interface to DSP Memory
Transfers from AC’97 data to DSP memory are accomplished
using DMA transfer through the DSP FIFOs. Each DSP has four
FIFOs available for data transfers to/from the AC’97 Codec
Interface. The registers that control FIFO DMA transfers are
only accessible from within the DSP and are defined as part of
the core register space.
Data FIFO Architecture
Each DSP core within the ADSP-2192M contains four FIFOs
which provide a data communication path to the rest of the chip.
Two of the FIFOs are input FIFOs, receiving data into the DSP.
The other two FIFOs are transmit FIFOs, sending data from the
DSP to the codec, AC’97 interface, or the other DSP. Each FIFO
is eight words deep and sixteen bits wide. Interrupts to the DSP
can be generated when some words have been received in the
input FIFOs, or when some words are empty in the
Transmit FIFOs.
The interface to the FIFOs on the DSP is simply a register
interface to the Peripheral Interface bus. TX0, RX0, TX1, and
RX1 are the primary FIFO registers in the DSP’s universal
register map. The FIFOs can be used to generate interrupts to
the DSP, based upon FIFO transactions, or they can initiate
DMA requests.
When communicating with the AC’97 interface, the Connection
Enable bits in the control register are set to 10. Bit 3 selects stereo
or mono transfers to and from the AC’97 interface. Bits 7–4
select the AC’97 slot associated with this FIFO.
When stereo is selected, the slot identified and the next slot are
both associated with the FIFO. Typically, stereo is selected for
left and right data, and both left and right must be associated with
the same external AC’97 codec and have their sample rates locked
together. In this case, left and right data will alternate in the FIFO
with the left data coming first.
If the FIFO is enabled for the AC’97 interface, and a valid request
for data comes along that the FIFO cannot fulfill, the transmitter
underflow bit is set, indicating that an invalid value was sent over
the selected slot. Similarly, on the receive side, if the FIFO is full
and another valid word is received, the Overflow bit is sent to
indicate the loss of data.
Table 24. Sub-ISA Indirect Access Registers
ISAA[3:1]
Name
Reset
Comments
0x0
0x1
0x2
0x3
0x5–0x4
Control Register Address
Reserved
Control Register Data
Reserved
DSP Memory Address
0x0000
0x0000
Address and direction control for register accesses
Data for register accesses
0x000000
Address and direction control for DSP memory
accesses
Data for DSP memory accesses.
0x7–0x6
DSP Memory Data
0x000000
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