參數(shù)資料
型號(hào)： ADSP-2192
廠商： Analog Devices, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： DSP Microcomputer
中文描述： DSP微機(jī)
文件頁數(shù)： 25/40頁
文件大?。?/td> 1307K
代理商： ADSP-2192
–25–
REV. 0
ADSP-2192M
Low Power Operation
In addition to supporting the PCI and USB standards’ power-
down modes, additional power-down modes for the DSP cores
and peripheral buses are supported by the ADSP-2192M. The
power-down modes are controlled by the DSP1 and DSP2 Inter-
rupt/Power-down registers.
Clock Signals
The ADSP-2192M can be clocked by a crystal oscillator. If a
crystal oscillator is used, the crystal should be connected across
the XTALI/O pins, with two capacitors connected as shown in
Figure 7
. Capacitor values are dependent on crystal type and
should be specified by the crystal manufacturer. A parallel-
resonant, fundamental frequency, microprocessor-grade
24.576 MHz crystal should be used for this configuration.
Figure 6. 2.5 V Regulator Options
+
–
VREF
IVDD
VCTRLVDD
VCTRLAUX
PCIVDD
3.0V – 5.5V
DSP
INTERNAL
CIRCUIT
EXTERNAL
COMPONENTS
2.5V @ 500mA
PCIVAUX
3.0V – 3.6V
ZETEX
FZT951
ZETEX
FZT951
TANTALUM
OR
ELECTROLYTIC
CERAMIC
10μF
0.1μF
Figure 7. External Crystal Connections
XTALI
XTALO
ADSP-2192M
CLKRUN
PORST
BUS0
BUS1
CLKSEL
BITCLK
24.576MHz
CLK
RST
3V OR 5V
CLOCK
BUS SELECT
POWR ON
RESET
PCI CLOCK RUN
PCI CLOCK
PCI RESET
AC'97 BIT
CLOCK
Figure 8. Clock Domains
DSP
CLOCK DOMAIN
X6
PLL
X4
PLL
USB
CLOCK
DOMAIN
24.576MHz
XTALI
147.456MHz
1/8.192 PLL AND
CLOCK RECOVERY
12.0MHz
1/2
BITCLK
AC’97
CLOCK DOMAIN
USB PORT
1/2
PERIPHERAL DEVICE
CONTROL BUS
CLOCK DOMAIN
12.288 MHz
PCI
CLOCK
DOMAIN
33MHz
PCI CLK
1/2
49.152MHz
49.152MHz
(SUB-ISA MODE)
(PROGRAMMABLE)
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