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參數(shù)資料
| 型號： | ADSP-2192 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | DSP微機 |
| 文件頁數(shù)： | 4/40頁 |
| 文件大?。?/td> | 1307K |
| 代理商： | ADSP-2192 |
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ADSP-2192M
–4–
REV. 0
the next cycle. For conditional or multifunction instructions,
there are restrictions on which data registers may provide inputs
or receive results from each computational unit. For more infor-
mation, see the ADSP-219x
DSP Instruction Set Reference
.
A powerful program sequencer controls the flow of instruction
execution. The sequencer supports conditional jumps, subrou-
tine calls, and low interrupt overhead. With internal loop
counters and loop stacks, the ADSP-219x core executes looped
code with zero overhead; no explicit jump instructions are
required to maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches. Each DAG maintains and
updates four 16-bit address pointers. Whenever the pointer is
used to access data (indirect addressing), it is pre- or post-
modified by the value of one of four possible modify registers. A
length value and base address may be associated with each pointer
to implement automatic modulo addressing for circular buffers.
Page registers in the DAGs allow linear or circular addressing
within 64K word boundaries of each of the memory pages, but
these buffers may not cross page boundaries. Secondary registers
duplicate all the primary registers in the DAGs; switching
between primary and secondary registers provides a fast context
switch.
Efficient data transfer in the core is achieved with the use of
internal buses:
Program Memory Address (PMA) Bus
Program Memory Data (PMD) Bus
Data Memory Address (DMA) Bus
Data Memory Data (DMD) Bus
Program memory can store both instructions and data, permit-
ting the ADSP-219x to fetch two operands in a single cycle, one
from program memory and one from data memory. The DSP’s
dual memory buses also let the ADSP-219x core fetch an operand
from data memory and the next instruction from program
memory in a single cycle.
DSP Peripherals
The Functional Block Diagram on Page 1 shows the DSP’s
on-chip peripherals, which include the Host port (PCI or USB),
AC’97 port, JTAG test and emulation port, flags, and interrupt
controller.
The ADSP-2192M can respond to up to thirteen interrupts at
any given time. A list of these interrupts appears in
Table 2
.
The AC’97 Codec port on the ADSP-2192M provides a
complete synchronous, full-duplex serial interface. This interface
supports the AC’97 standard.
The ADSP-2192M provides up to eight general-purpose I/O pins
that are programmable as either inputs or outputs. These pins
are dedicated general-purpose Programmable Flag pins.
The programmable interval timer generates periodic interrupts.
A 16-bit count register (TCOUNT) is decremented every
n cycles where n-1 is a scaling value stored in a 16-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Memory Architecture
The ADSP-2192M provides 132K words of on-chip SRAM
memory. This memory is divided into Program and Data
Memory blocks in each DSP’s memory map. In addition to the
internal memory space, the two cores can address two additional
and separate off-core memory spaces: I/O space and shared
memory space, as shown in
Figure 2
.
The ADSP-2192M’s two cores can access 80K and 48K locations
that are accessible through two 24-bit address buses, the PMA
and DMA buses.The DSP has three functions that support access
to the full memory map.
The DAGs generate 24-bit addresses for data fetches from
the entire DSP memory address range. Because DAG
index (address) registers are 16 bits wide and hold the
lower 16 bits of the address, each of the DAGs has its own
8-bit page register (DMPGx) to hold the most significant
eight address bits. Before a DAG generates an address,
the program must set the DAG’s DMPGx register to the
appropriate memory page.
The Program Sequencer generates the addresses for
instruction fetches. For relative addressing instructions,
the program sequencer bases addresses for relative jumps,
calls, and loops on the 24-bit Program Counter (PC). In
direct addressing instructions (two-word instructions),
the instruction provides an immediate 24-bit address
value. The PC allows linear addressing of the full 24-bit
address range.
For indirect jumps and calls that use a 16-bit DAG
address register for part of the branch address, the
Program Sequencer relies on an 8-bit Indirect Jump page
(IJPG) register to supply the most significant eight
address bits. Before a cross page jump or call, the program
must set the program sequencer’s IJPG register to the
appropriate memory page.
Each ADSP-219x DSP core has an on-chip ROM that holds boot
routines (
See Booting Modes on Page 23.
).
Interrupts
The interrupt controller lets the DSP respond to 13 interrupts
with minimum overhead. The controller implements an interrupt
priority scheme as shown in
Table 2
. Applications can use the
unassigned slots for software and peripheral interrupts. The
DSP’s Interrupt Control (ICNTL) register (shown in
Table 3
)
provides controls for global interrupt enable, stack interrupt con-
figuration, and interrupt nesting.
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