參數(shù)資料
型號: ADSP-2191
廠商: Analog Devices, Inc.
元件分類: 數(shù)字信號處理
英文描述: DSP Microcomputer
中文描述: DSP微機(jī)
文件頁數(shù): 14/52頁
文件大小: 1873K
代理商: ADSP-2191
ADSP-2191M
–14–
REV. 0
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide range
of tools supporting the ADSP-219x processor family. Hardware
tools include ADSP-219x PC plug-in cards. Third party software
tools include DSP libraries, real-time operating systems, and
block diagram design tools.
Designing an Emulator-Compatible DSP Board
(Target)
The White Mountain DSP (Product Line of Analog Devices,
Inc.) family of emulators are tools that every DSP developer
needs to test and debug hardware and software systems. Analog
Devices has supplied an IEEE 1149.1 JTAG Test Access Port
(TAP) on each JTAG DSP. The emulator uses the TAP to access
the internal features of the DSP, allowing the developer to load
code, set breakpoints, observe variables, observe memory, and
examine registers. The DSP must be halted to send data and
commands, but once an operation has been completed by the
emulator, the DSP system is set running at full speed with no
impact on system timing.
To use these emulators, the target’s design must include the
interface between an Analog Devices JTAG DSP and the
emulation header on a custom DSP target board.
Target Board Header
The emulator interface to an Analog Devices JTAG DSP is a
14-pin header, as shown in
Figure 4
. The customer must supply
this header on the target board in order to communicate with the
emulator. The interface consists of a standard dual row 0.025"
square post header, set on 0.1"
post length of 0.235". Pin 3 is the key position used to prevent
the pod from being inserted backwards. This pin must be clipped
on the target board.
Also, the clearance (length, width, and height) around the header
must be considered. Leave a clearance of at least 0.15" and 0.10"
around the length and width of the header, and reserve a height
clearance to attach and detach the pod connector.
0.1" spacing, with a minimum
As can be seen in
Figure 4
, there are two sets of signals on the
header. There are the standard JTAG signals TMS, TCK, TDI,
TDO,
TRST
, and
EMU
used for emulation purposes (via an
emulator). There are also secondary JTAG signals BTMS,
BTCK, BTDI, and
BTRST
that are optionally used for
board-level (boundary scan) testing.
When the emulator is not connected to this header, place jumpers
across BTMS, BTCK,
BTRST
, and BTDI as shown in
Figure 5
.
This holds the JTAG signals in the correct state to allow the DSP
to run free. Remove all the jumpers when connecting the
emulator to the JTAG header.
JTAG Emulator Pod Connector
Figure 6
details the dimensions of the JTAG pod connector at the
14-pin target end.
Figure 7
displays the keep-out area for a target
board header. The keep-out area allows the pod connector to
properly seat onto the target board header. This board area
should contain no components (chips, resistors, capacitors, etc.).
The dimensions are referenced to the center of the 0.25" square
post pin.
Figure 4. JTAG Target Board Connector for JTAG
Equipped Analog Devices DSP (Jumpers in
Place)
TOP VIEW
13
14
11
12
9
10
9
7
8
5
6
3
4
1
2
EMU
GND
TMS
TCK
TRST
TDI
TDO
GND
KEY (NO PIN)
BTMS
BTCK
BTRST
BTDI
GND
Figure 5. JTAG Target Board Connector with No Local
Boundary Scan
Figure 6. JTAG Pod Connector Dimensions
TOP VIEW
13
14
11
12
9
10
9
7
8
5
6
3
4
1
2
EMU
GND
TMS
TCK
TRST
TDI
TDO
GND
KEY (NO PIN)
BTMS
BTCK
BTRST
BTDI
GND
0.64"
0.88"
0.24"
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