參數(shù)資料
型號(hào)： ADSP-2191
廠商： Analog Devices, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： DSP Microcomputer
中文描述： DSP微機(jī)
文件頁(yè)數(shù)： 19/52頁(yè)
文件大?。?/td> 1873K
代理商： ADSP-2191
–19–
REV. 0
ADSP-2191M
ABSOLUTE MAXIMUM RATINGS
V
DDINT
Internal (Core) Supply Voltage
1,2
. . –0.3 V to 3.0 V
V
DDEXT
External (I/O) Supply Voltage . . . . –0.3 V to 4.6 V
V
IL
–V
IH
Input Voltage . . . . . . . . –0.5 V to V
DDEXT
+0.5 V
V
OL
–V
OH
Output Voltage Swing. –0.5 V to V
DDEXT
+0.5 V
T
STORE
Storage Temperature Range . . . . . .–65oC to 150oC
T
LEAD
Lead Temperature of ST-144 (5 seconds) . . . . 185oC
ESD SENSITIVITY
Power Dissipation
Using the operation-versus-current information in
Table 8
, designers can estimate the ADSP-2191M’s internal power supply
(V
DDINT
) input current for a specific application, according to the formula for I
DDINT
calculation beneath
Table 8
. For calculation
of external supply current and total supply current,
see Power Dissipation on page 41.
1
Specifications subject to change without notice.
2
Stresses greater than those listed above may cause permanent damage to the device.
These are stress ratings only; functional operation of the device at these or any
other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V
readily accumulate on the human body and test equipment and can discharge without
detection. Although the ADSP-2191M features proprietary ESD protection circuitry,
permanent damage may occur on devices subjected to high-energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid perfor-
mance degradation or loss of functionality.
Table 8. Operation Types Versus Input Current
K-Grade
I
DDINT
(mA) CCLK = 160 MHz
Core
Typ
1
Max
2
B-Grade
I
DDINT
(mA)
1
CCLK = 140 MHz
Core
Typ
1
Max
2
Peripheral
Typ
1
Peripheral
Typ
1
Activity
Power Down
3
Idle 1
4
Idle 2
5
Typical
6
Peak
7
1
Test conditions: V
DDINT
= 2.50 V; HCLK (peripheral clock) frequency = CCLK/2 (core clock/2) frequency; T
AMB
= 25oC.
2
Test conditions: V
DDINT
= 2.65 V; HCLK (peripheral clock) frequency = CCLK/2 (core clock/2) frequency; T
AMB
= 25oC.
3
PLL, Core, peripheral clocks, and CLKIN are disabled.
4
PLL is enabled and Core and peripheral clocks are disabled.
5
Core CLK is disabled and peripheral clock is enabled.
6
All instructions execute from internal memory. 50% of the instructions are repeat MACs with dual operand addressing, with changing data fetched using
a linear address sequence. 50% of the instructions are type 3 instructions.
7
All instructions execute from internal memory. 100% of the instructions are MACs with dual operand addressing, with changing data fetched using a linear
address sequence.
Max
2
Max
2
100μA
1
1
184
215
600μA
2
2
210
240
0
5
60
60
60
50μA
8
70
70
70
100μA
1
1
165
195
500μA
2
2
185
210
0
4
55
55
55
50μA
7
62
62
62
I
DDINT
%Typical
I
DDINT-TYPICAL
×
(
)
=
%Idle
I
DDINT-IDLE
×
(
)
%Power Down
I
DDINT-PWRDWN
×
(
)
+
+
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