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參數(shù)資料
| 型號： | ADSP-2191 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | DSP微機(jī) |
| 文件頁數(shù)： | 20/52頁 |
| 文件大?。?/td> | 1873K |
| 代理商： | ADSP-2191 |
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ADSP-2191M
TIMING SPECIFICATIONS
–20–
REV. 0
This section contains timing information for the DSP’s external signals. Use the exact information given. Do not attempt to derive
parameters from the addition or subtraction of other information. While addition or subtraction would yield meaningful results for an
individual device, the values given in this datasheet reflect statistical variations and worst cases. Consequently, parameters cannot be
added meaningfully to derive longer times.
Switching characteristics
specify how the processor changes its signals. No control is possible over this timing; circuitry external to the
processor must be designed for compatibility with these signal characteristics. Switching characteristics indicate what the processor
will do in a given circumstance. Switching characteristics can also be used to ensure that any timing requirement of a device connected
to the processor (such as memory) is satisfied.
Timing requirements
apply to signals that are controlled by circuitry external to the processor, such as the data input for a read
operation.Timing requirements guarantee that the processor operates correctly with other devices.
Clock In and Clock Out Cycle Timing
Table 9
and
Figure 8
describe clock and reset operations. Combinations of CLKIN and clock multipliers must not select core/periph-
eral clocks in excess of 160/80 MHz for commercial grade and 140/70 MHz for industrial grade, when the peripheral clock rate is
one-half the core clock rate. If the peripheral clock rate is equal to the core clock rate, the maximum peripheral clock rate is 80 MHz
for both commercial and industrial grade parts. The peripheral clock is supplied to the CLKOUT pins.
When changing from bypass mode to PLL mode, allow 512 HCLK cycles for the PLL to stabilize.
Table 9. Clock In and Clock Out Cycle Timing
Parameter
Min
Max
Unit
Switching Characteristics
t
CKOD
t
CKO
CLKOUT Delay from CLKIN
CLKOUT Period
1
0
12.5
5.8
ns
ns
1
CLKOUT jitter can be as great as 8 ns when CLKOUT frequency is less than 20 MHz. For frequencies greater than 20 MHz, jitter is less than 1 ns.
2
In clock multiplier mode and MSEL6–0 set for 1:1 (or CLKIN=CCLK), t
CK
=t
CCLK
.
3
In bypass mode, t
CK
=t
CCLK
.
Timing Requirements
t
CK
t
CKL
t
CKH
t
WRST
t
MSS
t
MSH
t
MSD
t
PFD
CLKIN Period
2,
3
CLKIN Low Pulse
CLKIN High Pulse
RESET
Asserted Pulsewidth Low
MSELx/BYPASS Stable Before
RESET
Deasserted Setup
MSELx/BYPASS Stable After
RESET
Deasserted Hold
MSELx/BYPASS Stable After
RESET
Asserted
Flag Output Disable Time After
RESET
Asserted
10
4.5
4.5
200t
CLKOUT
40
1000
200
ns
ns
ns
ns
μs
ns
ns
ns
200
10
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