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參數(shù)資料
| 型號： | ADSP-2191 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | DSP微機 |
| 文件頁數(shù)： | 42/52頁 |
| 文件大?。?/td> | 1873K |
| 代理商： | ADSP-2191 |
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ADSP-2191M
–42–
REV. 0
The output disable time t
DIS
is the difference between
t
MEASURED
and t
DECAY
as shown in
Figure 26
. The time
t
MEASURED
is the interval from when the reference signal
switches to when the output voltage decays –V from the measured
output high or output low voltage. The t
DECAY
is calculated with
test loads C
L
and I
L
, and with –V equal to 0.5 V.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start
driving. The output enable time t
ENA
is the interval from when
a reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram (
Figure 26
). If multiple
pins (such as the data bus) are enabled, the measurement value
is that of the first pin to start driving.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
DECAY
using the equation at
Output Disable Time
on page 41
. Choose –V to be the difference between the
ADSP-2191M’s output voltage and the input threshold for the
device requiring the hold time. A typical –V will be 0.4 V. C
L
is
the total bus capacitance (per data line), and I
L
is the total leakage
or three-state current (per data line). The hold time will be
t
DECAY
plus the minimum disable time (i.e., t
DATRWH
for the
write cycle).
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
50 pF on all pins (see
Figure 30
). The delay and hold specifica-
tions given should be derated by a factor of 1.5 ns/50 pF for loads
other than the nominal value of 50 pF.
Figure 28
and
Figure 29
show how output rise time varies with capacitance. These figures
also show graphically how output delays and holds vary with load
capacitance. (Note that this graph or derating does not apply to
output disable delays; see
Output Disable Time on page 41
.) The
graphs in these figures may not be linear outside the ranges
shown.
Environmental Conditions
The thermal characteristics in which the DSP is operating
influence performance.
Thermal Characteristics
The ADSP-2191M comes in a 144-lead LQFP or 144-lead Ball
Grid Array (mini-BGA) package. The ADSP-2191M is specified
for an ambient temperature (T
AMB
) as calculated using the
formula below.
To ensure that the T
AMB
data sheet specification is not exceeded,
a heatsink and/or an air flow source may be used. A heatsink
should be attached to the ground plane (as close as possible to
the thermal pathways) with a thermal adhesive.
Figure 26. Output Enable/Disable
Figure 27. Equivalent Device Loading for AC
Measurements (Includes All Fixtures)
Figure 28. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
REFERENCE
SIGNAL
t
DIS
OUTPUT STARTS
DRIVING
V
OH (MEASURED)
–
V
V
OL (MEASURED)
+
V
t
MEASURED
V
OH (MEASURED)
V
OL (MEASURED)
2.0V
1.0V
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS VOLTAGE
TO BE APPROXIMATELY 1.5V
OUTPUT STOPS
DRIVING
t
DECAY
t
ENA
+1.5V
50pF
TO
OUTPUT
PIN
I
OL
I
OH
INPUT
OR
OUTPUT
1.5V
1.5V
Figure 29. Typical Output Rise Time (10%-90%,
V
DDEXT
= Minimum at Maximum Ambient
Operating Temperature) vs. Load Capacitance
40
0
30
20
10
LOAD CAPACITANCE – pF
0
250
50
100
150
200
R
RISE TIME
T
AMB
T
CASE
=
PD
θ
CA
×
–
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