參數(shù)資料
型號: AD9957BSVZ
廠商: Analog Devices Inc
文件頁數(shù): 57/64頁
文件大?。?/td> 0K
描述: IC DDS 1GSPS 14BIT IQ 100TQFP
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝: 1
分辨率(位): 14 b
主 fclk: 1GHz
調(diào)節(jié)字寬(位): 32 b
電源電壓: 1.8V, 3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 100-TQFP-EP(14x14)
包裝: 托盤
產(chǎn)品目錄頁面: 552 (CN2011-ZH PDF)
配用: AD9957/PCBZ-ND - BOARD EVAL AD9957 QUADRATURE MOD
AD9957
Data Sheet
Rev. C | Page 60 of 64
PROFILE REGISTERS
There are eight consecutive serial I/O addresses (0x0E to 0x15)
dedicated to device profiles. All eight profile registers are either
single tone profiles or QDUC profiles depending on the device
operating mode specified by CFR1<25:24>. During operation,
the active profile register is determined via the external
PROFILE<2:0> pins.
Single tone profiles control: DDS frequency (32 bits), DDS
phase offset (16 bits), and DDS amplitude scaling (14 bits).
QDUC profiles control: DDS frequency (32 bits), DDS phase
offset (16 bits), output amplitude scaling (8 bits), CCI filter
interpolation factor, inverse CCI bypass, and spectral invert.
The QDUC profiles also selectively apply to the interpolating
DAC operating mode: only output scaling, CCI filter interpola-
tion factor, and inverse CCI bypass apply; all others (DDS
frequency, output amplitude scaling, and spectral invert) are
ignored.
Profile<7:0> Register—Single Tone
Address 0x0E to 0x15, eight bytes are assigned to this register.
Table 27. Bit Descriptions for Profile<7:0> Registers—Single Tone
Bit(s)
Mnemonic
Description
63:62
Open
61:48
Amplitude Scale Factor
This 14-bit number controls the DDS output amplitude.
47:32
Phase Offset Word
This 16-bit number controls the DDS phase offset.
31:0
Frequency Tuning Word
This 32-bit number controls the DDS frequency.
Profile<7:0> Register—QDUC
Address 0x0E to 0x15, eight bytes are assigned to this register.
Table 28. Bit Descriptions for Profile<7:0> Registers—QDUC
Bit(s)
Mnemonic
Description
63:58
CC Interpolation Rate
This 6-bit number is the rate interpolation factor for the CCI filter.
57
Spectral Invert
0: the modulator output takes the form: I(t) × cos(ct) – Q(t) × sin(ct).
1: the modulator output takes the form: I(t) × cos(ct) + Q(t) × sin(ct).
56
Inverse CCI Bypass
0: the inverse CCI filter is enabled.
1: the inverse CCI filter is bypassed.
55:48
Output Scale Factor
This 8-bit number controls the output amplitude.
47:32
Phase Offset Word
This 16-bit number controls the DDS phase offset.
31:0
Frequency Tuning Word
This 32-bit number controls the DDS frequency.
RAM Register
Address 0x16, four bytes are assigned to this register.
Table 29. Bit Descriptions for RAM Register
Bit(s)
Mnemonic
Description
31:0
RAM Word
The number of 32-bit words written to RAM is defined by the start and end address in
RAM Segment Register 0 or RAM Segment Register 1.
GPIO Configuration Register
Address 0x18, two bytes are assigned to this register.
Table 30. Bit Descriptions for GPIO Configuration Register
Bit(s)
Mnemonic
Description
15:0
GPIO Configuration
See the General-Purpose I/O (GPIO) Port section for details.
GPIO Data Register
Address 0x19, two bytes are assigned to this register.
Table 31. Bit Descriptions for GPIO Data Register
Bits
Mnemonic
Description
15:0
GPIO Data
Read or write based on the contents of the GPIO Configuration register. See the
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