參數(shù)資料
型號: AD9957BSVZ
廠商: Analog Devices Inc
文件頁數(shù): 54/64頁
文件大?。?/td> 0K
描述: IC DDS 1GSPS 14BIT IQ 100TQFP
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝: 1
分辨率(位): 14 b
主 fclk: 1GHz
調(diào)節(jié)字寬(位): 32 b
電源電壓: 1.8V, 3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 100-TQFP-EP(14x14)
包裝: 托盤
產(chǎn)品目錄頁面: 552 (CN2011-ZH PDF)
配用: AD9957/PCBZ-ND - BOARD EVAL AD9957 QUADRATURE MOD
AD9957
Data Sheet
Rev. C | Page 58 of 64
Control Function Register 3 (CFR3)
Address 0x02, four bytes are assigned to this register.
Table 20. Bit Descriptions for CFR3 Register
Bit (s)
Mnemonic
Description
31:30
Open
29:28
DRV0
Controls REFCLK_OUT pin (see Table 6 for details); default is 01b.
27
Open
26:24
VCO SEL
Selects frequency band of the VCO in the REFCLK PLL (see Table 7 for details); default is 111b.
23:22
Open
21:19
ICP
Selects the charge pump current in the REFCLK PLL (see Table 8 for details); default is 111b.
18:16
Open
15
REFCLK Input Divider
Bypass
0: input divider is selected (default).
1: input divider is bypassed.
14
REFCLK Input Divider
ResetB
0: input divider is reset.
1: input divider operates normally (default).
13:9
Open
8
PLL Enable
0: REFCLK PLL bypassed (default).
1: REFCLK PLL enabled.
7:1
N
This 7-bit number is divide modulus of the REFCLK PLL feedback divider; default is 0000000b.
0
Open
Auxiliary DAC Control Register
Address 0x03, four bytes are assigned to this register.
Table 21. Bit Descriptions for Auxiliary DAC Control Register
Bit(s)
Mnemonic
Description
31:8
Open
7:0
FSC
This 8-bit number controls the full-scale output current of the main DAC (see the Auxiliary DAC section);
default is 0xFF.
I/O Update Rate Register
Address 0x04, four bytes are assigned to this register. This register is effective without the need for an I/O update.
Table 22. Bit Descriptions for I/O Update Rate Register5
Bit(s)
Mnemonic
Description
31:0
I/O Update Rate
Ineffective unless CFR2<23> = 1. This 32-bit number controls the automatic I/O update rate (see the
Automatic I/O Update section); default is 0xFFFFFFFF.
RAM Segment Register 0
Address 0x05, six bytes are assigned to this register. This register is effective without the need for an I/O update. This register is only
active if CFR1<31> = 1 and there is a Logic 0-to-Logic 1 transition on the RT pin.
Table 23. Bit Descriptions for RAM Segment Register 0
Bit(s)
Mnemonic
Description
47:32
RAM Address Step
Rate 0
This 16-bit number controls the rate at which the RAM state machine steps through the specified RAM
address range.
31:22
RAM End Address 0
This 10-bit number identifies the ending address for the RAM state machine.
21:16
Open
15:6
RAM Start Address 0
This 10-bit number identifies the starting address for the RAM state machine.
5:3
Open
2:0
RAM Playback Mode 0
This 3-bit number identifies the playback mode for the RAM state machine (see Table 5).
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