參數(shù)資料
型號(hào)： AD9957BSVZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 52/64頁(yè)
文件大小： 0K
描述： IC DDS 1GSPS 14BIT IQ 100TQFP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝： 1
分辨率（位）： 14 b
主 fclk： 1GHz
調(diào)節(jié)字寬（位）： 32 b
電源電壓： 1.8V, 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 552 (CN2011-ZH PDF)
配用： AD9957/PCBZ-ND - BOARD EVAL AD9957 QUADRATURE MOD
AD9957
Data Sheet
Rev. C | Page 56 of 64
Bit (s)
Mnemonic
Description
9
OSK (Output Shift
Keying) Enable
0: OSK disabled (default).
1: OSK enabled.
8
Select Auto-OSK
Ineffective unless CFR1<9> = 1.
0: manual OSK enabled (default).
1: automatic OSK enabled.
7
Digital Power-
Down
This bit is effective without the need for an I/O update.
0: clock signals to the digital core are active (default).
1: clock signals to the digital core are disabled.
6
DAC Power-Down
0: DAC clock signals and bias circuits are active (default).
1: DAC clock signals and bias circuits are disabled.
5
REFCLK Input
Power-Down
This bit is effective without the need for an I/O update.
0: REFCLK input circuits and PLL are active (default).
1: REFCLK input circuits and PLL are disabled.
4
Auxiliary DAC
Power-Down
0: auxiliary DAC clock signals and bias circuits are active (default).
1: auxiliary DAC clock signals and bias circuits are disabled.
3
External Power-
Down Control
0: assertion of the EXT_PWR_DWN pin affects full power-down (default).
1: assertion of the EXT_PWR_DWN pin affects fast recovery power-down.
2
Auto Power-Down
Enable
Ineffective when CFR1<25:24> = 01b.
0: disable power-down (default).
1: when the TxEnable pin is Logic 0, the baseband signal processing chain is flushed of residual data and
the clocks are automatically stopped. Clocks restart when the TxENABLE pin is a Logic 1.
1
SDIO Input Only
0: configures the SDIO pin for bidirectional operation; 2-wire serial programming mode (default).
1: configures the serial data I/O pin (SDIO) as an input only pin; 3-wire serial programming mode.
0
LSB First
0: configures the serial I/O port for MSB first format (default).
1: configures the serial I/O port for LSB first format.
Control Function Register 2 (CFR2)
Address 0x01, four bytes are assigned to this register.
Table 19. Bit Descriptions for CFR2 Register
Bit (s)
Mnemonic
Description
31
Blackfin Interface
Mode Active
Valid only when CFR1<25:24> = 00b (quadrature modulation mode).
0: Pin D<17:0> configured as an 18-bit parallel port (default).
1: Pin D<5:4> configured as a dual serial port compatible with the Blackfin serial interface. Pin D<17:6>
and Pin D<3:0> become available as a 16-bit GPIO port.
30
Blackfin Bit Order
Valid only when CFR2<31> = 1.
0: the dual serial port (BFI) configured for MSB first operation (default).
1: the dual serial port (BFI) configured for LSB first operation.
29
Blackfin Early
Frame Sync
Enable
Valid only when CFR2<31> = 1.
0: the dual serial port (BFI) configured to be compatible with Blackfin late frame sync operation (default).
1: the dual serial port (BFI) configured to be compatible with Blackfin early frame sync operation.
28:25
Open
24
Enable Profile
Registers as ASF
Source
Valid only when CFR1<25:24> = 01b (single tone mode) and CFR1<9>=0 (OSK disabled).
0: amplitude scale factor bypassed (unity gain).
1: the active profile register determines the amplitude scale factor.
23
Internal I/O
Update Active
This bit is effective without the need for an I/O update.
0: serial I/O programming is synchronized with external assertion of the I/O_UPDATE pin, which is
configured as an input pin (default).
1: serial I/O programming is synchronized with an internally generated I/O update signal (the internally
generated signal appears at the I/O_UPDATE pin, which is configured as an output pin).
22
SYNC_CLK Enable
0: the SYNC_CLK pin is disabled; static Logic 0 output.
1: the SYNC_CLK pin generates a clock signal at fSYSCLK; use of synchronization of the serial I/O port
(default).
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AD9957BSVZ-REEL 功能描述:IC DDS 1GSPS 14BIT IQ 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
AD9957BSVZREEL13 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC
AD9958 制造商:AD 制造商全稱:Analog Devices 功能描述:2-Channel 500 MSPS DDS with 10-Bit DACs
AD9958 PCB 制造商:Analog Devices 功能描述:EVAL BOARD ((NS))
AD9958/PCB 制造商:Analog Devices 功能描述:Evaluation Board For 2-Channel 500 MSPS DDS With 10-Bit DACs 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:IC 10-BIT DAC DDS
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