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參數(shù)資料
| 型號： | AD9957BSVZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 53/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DDS 1GSPS 14BIT IQ 100TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 分辨率（位）： | 14 b |
| 主 fclk： | 1GHz |
| 調(diào)節(jié)字寬（位）： | 32 b |
| 電源電壓： | 1.8V, 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 552 (CN2011-ZH PDF) |
| 配用： | AD9957/PCBZ-ND - BOARD EVAL AD9957 QUADRATURE MOD |
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Data Sheet
AD9957
Rev. C | Page 57 of 64
Bit (s)
Mnemonic
Description
21:17
Open
16
Read Effective
FTW
0: a serial I/O port read operation of the FTW register reports the contents of the FTW register (default).
1: a serial I/O port read operation of the FTW register reports the actual 32-bit word appearing at the input to
the DDS phase accumulator.
15:14
I/O Update Rate
Control
Ineffective unless CFR2<23> = 1. Sets the prescale ratio of the divider that clocks the I/O update timer as
follows:
00: divide-by-1 (default).
01: divide-by-2.
10: divide-by-4.
11: divide-by-8.
13
PDCLK Rate
Control
Ineffective unless CFR2<31> = 0 and CFR1<25:24> = 00b.
0: PDCLK operates at the input data rate (default).
1: PDCLK operates at the input data rate; useful for maintaining a consistent relationship between I/Q
words at the parallel data port and the internal clocks of the baseband signal processing chain.
12
Data Format
0: the data-words applied to Pin D<17:0> are expected to be coded as twos complement (default).
1: the data-words applied to Pin D<17:0> are expected to be coded as offset binary.
11
PDCLK Enable
0: the PDCLK pin is disabled and forced to a static Logic 0 state; the internal clock signal continues to operate
and provide timing to the data assembler.
1: the internal PDCLK signal appears at the PDCLK pin (default).
10
PDCLK Invert
0: normal PDCLK polarity; Q-data associated with Logic 1, I-data with Logic 0 (default).
1: inverted PDCLK polarity.
9
TxEnable Invert
0: normal TxENABLE polarity; Logic 0 is standby, Logic 1 is transmit (default).
1: inverted TxENABLE polarity; Logic 0 is transmit, Logic 1 is standby.
8
Q-First Data
Pairing
0: an I/Q data pair is delivered as I-data first, followed by Q-data (default).
1: an I/Q data pair is delivered as Q-data first, followed by I-data.
7
Open
6
Data Assembler
Hold Last Value
Ineffective when CFR1<25:24> = 01b.
0: when the TxENABLE pin is false, the data assembler ignores the input data and internally forces zeros on
the baseband signal path (default).
1: when the TxENABLE pin is false, the data assembler ignores the input data and internally forces the last
value received on the baseband signal path.
5
Sync Timing
Validation Disable
0: enables the setup and hold validation circuit to take a measurement; the measurement result appears at
the SYNC_SMP_ERR pin; a Logic 1 at this pin indicates a potential setup/hold violation whereas a Logic 0
indicates that a setup/hold violation has not been detected; the measurement result is latched and held until
this bit is set to a Logic 1.
1: resets the setup and hold validation measurement circuit forcing the SYNC_SMP_ERR pin to a static Logic 0
condition (default); the measurement circuit is effectively disabled until this bit is restored to a Logic 0 state.
4:0
Open
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| AD9957BSVZ-REEL | 功能描述:IC DDS 1GSPS 14BIT IQ 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9957BSVZREEL13 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC |
| AD9958 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2-Channel 500 MSPS DDS with 10-Bit DACs |
| AD9958 PCB | 制造商:Analog Devices 功能描述:EVAL BOARD ((NS)) |
| AD9958/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For 2-Channel 500 MSPS DDS With 10-Bit DACs 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:IC 10-BIT DAC DDS |
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