參數(shù)資料
型號(hào): AD9957BSVZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 19/64頁(yè)
文件大?。?/td> 0K
描述: IC DDS 1GSPS 14BIT IQ 100TQFP
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝: 1
分辨率(位): 14 b
主 fclk: 1GHz
調(diào)節(jié)字寬(位): 32 b
電源電壓: 1.8V, 3.3V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 100-TQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 100-TQFP-EP(14x14)
包裝: 托盤(pán)
產(chǎn)品目錄頁(yè)面: 552 (CN2011-ZH PDF)
配用: AD9957/PCBZ-ND - BOARD EVAL AD9957 QUADRATURE MOD
AD9957
Data Sheet
Rev. C | Page 26 of 64
In Figure 37, it can be seen that the sinc envelope introduces a
frequency dependent attenuation that can be as much as 4 dB at
the Nyquist frequency (half of the DAC sample rate). Without
the inverse sinc filter, the DAC output also suffers from the
frequency dependent droop of the sinc envelope. The inverse
sinc filter effectively flattens the droop to within ±0.05 dB as
shown in Figure 38, which shows the corrected sinc response
with the inverse sinc filter enabled.
1
0
–1
–2
–3
–4
0
0.1
0.2
0.4
0.3
0.5
06384-
017
(d
B)
FREQUENCY RELATIVE TO DAC SAMPLE RATE
INVERSE
SINC
Figure 37. Sinc and Inverse Sinc Responses
–2.8
–2.9
–3.0
–3.1
0
0.1
0.2
0.4
0.3
0.5
06384-
018
(d
B)
FREQUENCY RELATIVE TO DAC SAMPLE RATE
COMPENSATED RESPONSE
Figure 38. DAC Response with Inverse Sinc Compensation
OUTPUT SCALE FACTOR (OSF)
In QDUC and interpolating DAC modes, the output amplitude
is controlled using an 8-bit digital multiplier. The 8-bit multiplier
value is called the output scale factor (OSF) and is programmed
via the appropriate control registers. It is available for each of
the eight profiles. The LSB weight is 27, which yields a multiplier
range of 0 to 1.9921875 (2 27). The gain extends to nearly a
factor of 2 to provide a means to overcome the intrinsic loss
through the modulator when operating in the quadrature
modulation mode.
In interpolating DAC mode, the OSF should not be programmed
to exceed unity, as clipping can result. Programming the 8-bit
multiplier to unity gain (0x80) bypasses the stage and reduces
power consumption.
14-BIT DAC
The AD9957 incorporates an integrated 14-bit current-output
DAC. The output current is delivered as a balanced signal using
two outputs. The use of balanced outputs reduces the amount of
common-mode noise at the DAC output, increasing signal-to-
noise ratio. An external resistor (RSET) connected between the
DAC_RSET pin and AGND establishes a reference current. The
full-scale output current of the DAC (IOUT) is a scaled version of
the reference current (see the Auxiliary DAC section that
follows).
Proper attention should be paid to the load termination to keep
the output voltage within the specified compliance range, as
voltages developed beyond this range cause excessive distortion
and can damage the DAC output circuitry.
Auxiliary DAC
The full-scale output current of the main DAC (IOUT) is con-
trolled by an 8-bit auxiliary DAC. An 8-bit code word stored in
the appropriate register map location sets IOUT according to the
following equation:
+
=
96
1
4
.
86
CODE
R
I
SET
OUT
(6)
where:
RSET is the value of the RSET resistor (in ohms).
CODE is the 8-bit value supplied to the auxiliary DAC (default
is 127).
For example, with RSET = 10,000 and CODE = 127, IOUT = 20.07 mA.
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