參數(shù)資料
型號(hào): AD9957BSVZ
廠(chǎng)商: Analog Devices Inc
文件頁(yè)數(shù): 46/64頁(yè)
文件大?。?/td> 0K
描述: IC DDS 1GSPS 14BIT IQ 100TQFP
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝: 1
分辨率(位): 14 b
主 fclk: 1GHz
調(diào)節(jié)字寬(位): 32 b
電源電壓: 1.8V, 3.3V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 100-TQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 100-TQFP-EP(14x14)
包裝: 托盤(pán)
產(chǎn)品目錄頁(yè)面: 552 (CN2011-ZH PDF)
配用: AD9957/PCBZ-ND - BOARD EVAL AD9957 QUADRATURE MOD
AD9957
Data Sheet
Rev. C | Page 50 of 64
REGISTER MAP AND BIT DESCRIPTIONS
REGISTER MAP
Note that the highest number found in the Bit Range column for each register in the following tables is the MSB and the lowest number is
the LSB for that register.
Table 13. Control Registers
Register
Name
(Serial
Address)
Bit
Range
(Internal
Address)
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
Control
Function
Register 1
CFR1
(0x00)
<31:24>
RAM
Enable
Open
RAM
Playback
Destination
Open
Operating Mode
0x00
<23:16>
Manual
OSK
External
Control
Inverse
Sinc Filter
Enable
Clear CCI
Open
Select
DDS
Sine
Output
0x00
<15:8>
Open
Autoclear
Phase
Accumulator
Open
Clear Phase
Accumulator
Load ARR @
I/O Update
OSK
Enable
Select
Auto-
OSK
0x00
<7:0>
Digital
Power-
Down
DAC Power-
Down
REFCLK Input
Power-Down
Aux DAC
Power-Down
External
Power-Down
Control
Auto
Power-Down
Enable
SDIO
Input
Only
LSB First
0x00
Control
Function
Register 2
CFR2
(0x01)
<31:24>
Blackfin
Interface
Mode
Active
Blackfin Bit
Order
Blackfin
Early Frame
Sync Enable
Open
Enable
Profile
Registers
as ASF
Source
0x00
<23:16>
Internal
I/O
Update
Active
SYNC_CLK
Enable
Open
Read
Effective
FTW
0x40
<15:8>
I/O Update Rate Control
PDCLK Rate
Control
Data Format
PDCLK
Enable
PDCLK
Invert
TxEnable
Invert
Q-First
Data
Pairing
0x08
<7:0>
Open
Data
Assembler
Hold Last
Value
Sync Timing
Validation
Disable
Open
0x20
Control
Function
Register 3
CFR3
(0x02)
<31:24>
Open
DRV0<1:0>
Open
VCO SEL<2:0>
0x1F
<23:16>
Open
ICP<2:0>
Open
0x3F
<15:8>
REFCLK
Input
Divider
Bypass
REFCLK
Input
Divider
ResetB
Open
PLL
Enable
0x40
<7:0>
N<6:0>
Open
0x00
Auxiliary
DAC
Control
Register
(0x03)
<31:24>
Open
0x00
<23:16>
Open
0x00
<15:8>
Open
0x7F
<7:0>
FSC<7:0>
0x7F
I/O Update
Rate
Register
(0x04)
<31:24>
I/O Update Rate<31:24>
0xFF
<23:16>
I/O Update Rate<23:16>
0xFF
<15:8>
I/O Update Rate<15:8>
0xFF
<7:0>
I/O Update Rate<7:0>
0xFF
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