參數(shù)資料
型號: AD9957BSVZ
廠商: Analog Devices Inc
文件頁數(shù): 11/64頁
文件大?。?/td> 0K
描述: IC DDS 1GSPS 14BIT IQ 100TQFP
產(chǎn)品培訓模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標準包裝: 1
分辨率(位): 14 b
主 fclk: 1GHz
調節(jié)字寬(位): 32 b
電源電壓: 1.8V, 3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-TQFP 裸露焊盤
供應商設備封裝: 100-TQFP-EP(14x14)
包裝: 托盤
產(chǎn)品目錄頁面: 552 (CN2011-ZH PDF)
配用: AD9957/PCBZ-ND - BOARD EVAL AD9957 QUADRATURE MOD
Data Sheet
AD9957
Rev. C | Page 19 of 64
INTERPOLATING DAC MODE
A block diagram of the AD9957 operating in interpolating DAC
mode is shown in Figure 28; grayed items are inactive. In this
mode, the Q data path, DDS, and modulator are all disabled; only
the I data path is active.
As in quadrature modulation mode, the PDCLK pin functions
as a clock, synchronizing the input of data to the AD9957.
No modulation takes place in the interpolating DAC mode;
therefore, the spectrum of the data supplied at the parallel port
remains at baseband. However, a sample rate conversion takes
place based on the programmed interpolation rate. The inter-
polation hardware processes the signal, effectively performing
an oversample with a zero-stuffing operation. The original
input spectrum remains intact and the images that otherwise
would occur from the sample rate conversion process are
suppressed by the interpolation signal chain.
06384-
008
PDCLK
I/Q IN
E
X
T
_P
W
R_DW
N
DAC_RSET
IOUT
TxENABLE
DAC GAIN
θ
IN
VER
SE
S
INC
FILTE
R
CLOCK
FTW
PW
8
SYSCLK
PLL
÷2
CL
O
CK
M
O
DE
REF_CLK
REFCLK_OUT
XTAL_SEL
PARALLEL DATA
TIMING AND CONTROL
AD9957
ω
cos (ωt+θ)
sin (ωt+θ)
S
Y
NC_O
UT
S
Y
NC_I
N
P
LL_
LOC
K
P
LL_
LOOP
_
FI
L
T
ER
MA
ST
ER
_
R
ESET
2
DDS
AUX
DAC
8-BIT
POWER
DOWN
CONTROL
18
D
AT
A
SSEMB
L
ER
AND
F
O
RM
A
TTE
R
I
Q
IS
QS
BL
ACKF
IN
I
NT
E
R
F
ACE
18
16
HAL
F
-BAND
FI
L
T
ER
S
(4
×
)
IN
VER
SE
CCI
(1×
T
O
63×
)
HAL
F
-BAND
FI
L
T
ER
S
(4
×
)
IN
VER
SE
CCI
(1×
T
O
63×
)
OSK
INTERNAL CLOCK TIMING AND CONTROL
DAC
14-BIT
FTW
PW
O
SK
RT
RAM
P
R
OFILE
SERIAL I/O
PORT
I/O_
U
P
D
A
TE
PROGRAMMING
REGISTERS
3
I Q
IS QS
OUTPUT
SCALE
FACTOR
CCI
_O
V
F
L
S
DI
O
CS
I/
O
_
R
ESET
S
CL
K
S
DO
Figure 28. Interpolating DAC Mode
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