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參數(shù)資料
| 型號： | AD9957BSVZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DDS 1GSPS 14BIT IQ 100TQFP |
| 產(chǎn)品培訓模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 標準包裝： | 1 |
| 分辨率（位）： | 14 b |
| 主 fclk： | 1GHz |
| 調(diào)節(jié)字寬（位）： | 32 b |
| 電源電壓： | 1.8V, 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 552 (CN2011-ZH PDF) |
| 配用： | AD9957/PCBZ-ND - BOARD EVAL AD9957 QUADRATURE MOD |
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AD9957
Data Sheet
Rev. C | Page 28 of 64
LOAD/RETRIEVE RAM OPERATION
Loading or retrieving the RAM contents is a three-step process.
1. Program the RAM segment registers with start and end
addresses defining the boundaries of each independent
RAM segment.
2. Toggle the RT pin with the appropriate transition to select
the desired RAM segment register.
3. Using the serial I/O port, write (or read) the address range
specified by the selected RAM segment register.
Figure 40 shows the RAM block diagram when used for loading
or retrieve operations.
RAM
32
10
Q
STATE
MACHINE
RT
END ADDRESS
START ADDRESS
10
ADDRESS STEP RATE
16
RAM MODE
3
CLK
BASEBAND DATA CLOCK
I
16
IS
Q
QS
DDS CLOCK
UP/DOWN COUNTER
I CHANNEL
Q CHANNEL
S
E
R
IA
L
I/O
P
OR
T
ADDRE
S
DAT
A
U/D
32
(MSBs)
(LSBs)
16
06384-
020
NOTES
1. NONESSENTIAL FUNCTIONAL COMPONENTS ARE RENDERED IN GRAY.
RAM
SEGMENT
REGISTERS
SCLK
SDIO
SDO
CS
I/O_RESET
Figure 40. RAM Load/Retrieve Operation
During a load or retrieve operation, the state machine controls
an up/down counter to step through the required RAM locations.
The counter is synchronized with the serial I/O port so that the
serial/parallel conversion of the 32-bit words is correctly timed
with the generation of the appropriate RAM address to properly
execute the desired read or write operation. The up/down
counter always increments through the address range during
serial I/O port operations.
Because the RAM segment registers are completely independent,
it is possible to define overlapping address ranges. However,
doing so causes the overlapping address locations to be over-
written by the most recent write operation. It is recommended
that the user avoid defining overlapping address ranges.
RAM PLAYBACK OPERATION
When the RAM has been loaded, it can be used for playback
operation. The destination of the playback data is selected via
the RAM playback destination bit. The active RAM segment
register is selected by the appropriate transition of the RT pin.
The active RAM segment register directs the internal state
machine by defining the RAM address range occupied by the
data and the RAM playback mode. It also defines the playback
rate when the playback destination is the baseband scaling
multipliers.
Although RAM load/retrieve operations via the serial I/O port
take precedence over playback, it is recommended that the user
not attempt RAM access via the serial I/O port when the RAM
enable bit is set.
Figure 41 is a block diagram showing the functional compo-
nents used for RAM playback operation when the internal
destination is the baseband scaling multipliers.
RAM
32
10
Q
STATE
MACHINE
RT
END ADDRESS
START ADDRESS
10
ADDRESS STEP RATE
16
RAM MODE
3
CLK
BASEBAND DATA CLOCK
I
16
IS
Q
QS
DDS CLOCK
UP/DOWN COUNTER
I CHANNEL
Q CHANNEL
RAM
SEGMENT
REGISTERS
S
E
R
IA
L
I/O
P
OR
T
ADDRE
S
DAT
A
U/D
32
(MSBs)
(LSBs)
16
06384-
021
NOTES
1. NONESSENTIAL FUNCTIONAL COMPONENTS ARE RENDERED IN GRAY.
SCLK
SDIO
SDO
CS
I/O_RESET
Figure 41. RAM Playback to Baseband Scaling Multipliers
During playback to the baseband scaling multipliers, the
address step rate word in the active RAM segment register sets
the rate at which RAM data samples are delivered to the
multipliers. The following equations define the RAM sample
rate and sample interval (Δt):
RM
f
Rate
Sample
RAM
SYSCLK
4
=
SYSCLK
f
RM
t
4
=
where:
R is the rate interpolation factor for the CCI filter.
M is the 16-bit value of the address step rate word stored in the
active RAM segment register.
If the RAM enable bit is set and the baseband scaling multi-
pliers are selected as the playback destination, then assertion
of an I/O update or profile change causes the multipliers to be
driven with a static value of zero. A subsequent state change on
the RT pin causes the multipliers to be driven by the data played
back from the RAM instead of the static zero value.
Figure 42 is a block diagram showing RAM playback operation
when the internal destination is the baseband data path. During
playback to the baseband data path, the state machine increments/
decrements the RAM address at the baseband data rate (the
address step rate must be set to 1).
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| AD9957BSVZ-REEL | 功能描述:IC DDS 1GSPS 14BIT IQ 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9957BSVZREEL13 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC |
| AD9958 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2-Channel 500 MSPS DDS with 10-Bit DACs |
| AD9958 PCB | 制造商:Analog Devices 功能描述:EVAL BOARD ((NS)) |
| AD9958/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For 2-Channel 500 MSPS DDS With 10-Bit DACs 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:IC 10-BIT DAC DDS |
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