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| 型號： | AD9957BSVZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 31/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DDS 1GSPS 14BIT IQ 100TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 分辨率（位）： | 14 b |
| 主 fclk： | 1GHz |
| 調(diào)節(jié)字寬（位）： | 32 b |
| 電源電壓： | 1.8V, 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 552 (CN2011-ZH PDF) |
| 配用： | AD9957/PCBZ-ND - BOARD EVAL AD9957 QUADRATURE MOD |
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Data Sheet
AD9957
Rev. C | Page 37 of 64
ADDITIONAL FEATURES
OUTPUT SHIFT KEYING (OSK)
The OSK function (Figure 53) is only available in single tone
mode. It allows the user to control the output signal amplitude
of the DDS. Both manual and automatic modes are available.
06384-
031
OSK ENABLE
AMPLITUDE SCALE FACTOR
(ASF<15:2>)
AMPLITUDE RAMP RATE
(ASF<31:16>)
AMPLITUDE STEP SIZE
(ASF<1:0>)
MANUAL OSK EXTERNAL
AUTO OSK ENABLE
OSK
DDS CLOCK
TO DDS
AMPLITUDE
CONTROL
PARAMETER
60
LOAD ARR AT I/O_UPDATE
OSK
CONTROLLER
14
16
14
2
Figure 53. OSK Block Diagram
The operation of the OSK function is governed by four control
register bits, the external OSK pin, and the entire 32 bits of the
ASF register. The primary control for the OSK block is the OSK
enable bit. When this bit is set, the OSK function is enabled;
otherwise, the OSK function is disabled. When disabled, the
other OSK input controls are ignored and the internal clocks are
shut down to conserve power.
When the OSK function is enabled, automatic and manual
operation is selected via the Select Auto-OSK bit. When this bit
is set, the automatic mode is active; otherwise, the manual
mode is active.
Manual OSK
In manual mode, output amplitude is varied by successive write
operations to the amplitude scale factor portion of the ASF
register. The rate at which amplitude changes can be applied to
the output signal is limited by the speed of the serial I/O port.
In manual mode, the OSK pin functionality depends on the
state of the manual OSK external control bit. It is either inoperative
or used to switch the output amplitude between the programmed
amplitude scale factor value and zero. When operational, a Logic 0
on the OSK pin forces the output amplitude to zero whereas a
Logic 1 on the OSK pin causes the output amplitude to be scaled
by the amplitude scale factor value.
Automatic OSK
In automatic mode, the OSK function automatically generates
a linear amplitude vs. time profile (or amplitude ramp). The
amplitude ramp is controlled via three parameters, as follows:
The maximum amplitude scale factor
The amplitude step size
The time interval between steps
The amplitude ramp parameters reside in the 32-bit ASF
register and are programmed via the serial I/O port. The
amplitude step interval is set using the 16-bit amplitude ramp
rate portion of the ASF register (Bits<31:16>). The maximum
amplitude scale factor is set using the 14-bit amplitude scale
factor in the ASF register (Bits<15:2>). The amplitude step size
is set using the 2-bit amplitude step size portion of the ASF
register (Bits<1:0>). The direction of the ramp (positive or
negative slope) is controlled by the external OSK pin. When
the OSK pin is a Logic 1, the slope is positive; otherwise, it is
negative.
The step interval is controlled by a 16-bit programmable timer
that is clocked at a rate of fSYSCLK. The timer period sets the
interval between amplitude steps. The step time interval (Δt)
is given by
SYSCLK
f
M
t
4
=
where M is the 16-bit number stored in the amplitude ramp rate
portion of the ASF register. For example, if fSYSCLK = 750 MHz
and M = 23,218 (0x5AB2), then Δt ≈ 123.8293 μs.
The output of the OSK function is a 14-bit unsigned data bus
that controls the amplitude of the DDS output (as long as the
OSK enable bit is Logic 1). When the OSK pin is Logic 1, the
OSK output value starts at 0 and increments by the programmed
amplitude step size until it reaches the programmed maximum
amplitude value. When the OSK pin is Logic 0, the OSK output
starts at its present value and decrements by the programmed
amplitude step size until it reaches 0.
The OSK output does not necessarily attain the maximum
amplitude—the OSK pin may switch to Logic 0 before attaining
the maximum value.
The OSK output does not necessarily reach a value of zero—the
OSK pin may switch to Logic 1 before attaining the zero value.
The OSK output is initialized to 0 at power-up. It is also set to 0
when the OSK enable bit is Logic 0 or when the OSK enable bit
is Logic 1, but the Select Auto-OSK bit is Logic 0.
The amplitude step size of the OSK output is set by the ampli-
tude step size bits in the ASF register according to the values
listed in Table 9. The step size refers to the LSB weight of the
14-bit OSK output.
The OSK output cannot exceed the maximum amplitude value
programmed into the ASF register.
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| AD9957BSVZ-REEL | 功能描述:IC DDS 1GSPS 14BIT IQ 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9957BSVZREEL13 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC |
| AD9958 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2-Channel 500 MSPS DDS with 10-Bit DACs |
| AD9958 PCB | 制造商:Analog Devices 功能描述:EVAL BOARD ((NS)) |
| AD9958/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For 2-Channel 500 MSPS DDS With 10-Bit DACs 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:IC 10-BIT DAC DDS |
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