參數(shù)資料
型號: AD9957BSVZ
廠商: Analog Devices Inc
文件頁數(shù): 43/64頁
文件大?。?/td> 0K
描述: IC DDS 1GSPS 14BIT IQ 100TQFP
產品培訓模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標準包裝: 1
分辨率(位): 14 b
主 fclk: 1GHz
調節(jié)字寬(位): 32 b
電源電壓: 1.8V, 3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-TQFP 裸露焊盤
供應商設備封裝: 100-TQFP-EP(14x14)
包裝: 托盤
產品目錄頁面: 552 (CN2011-ZH PDF)
配用: AD9957/PCBZ-ND - BOARD EVAL AD9957 QUADRATURE MOD
AD9957
Data Sheet
Rev. C | Page 48 of 64
SDO—Serial Data Out
Data is read from this pin for protocols that use separate lines
for transmitting and receiving data. In the case where the
AD9957 operates in a single bidirectional I/O mode, this pin
does not output data and is set to a high impedance state.
I/O_RESET—Input/Output Reset
I/O_RESET synchronizes the I/O port state machines without
affecting the addressable registers contents. An active high
input on the I/O_RESET pin causes the current communication
cycle to abort. After I/O_RESET returns low (Logic 0), another
communication cycle can begin, starting with the instruction
byte write.
I/O_UPDATE—Input/Output Update
The I/O_UPDATE initiates the transfer of written data from
the I/O port buffer to active registers. I/O_UPDATE is active
on the rising edge and its pulse width must be greater than one
SYNC_CLK period. It is either an input or output pin depending
on the programming of the Internal I/O Update Active bit.
SERIAL I/O TIMING DIAGRAMS
Figure 60 through Figure 63 provide basic examples of the tim-
ing relationships between the various control signals of the serial
I/O port. Most of the bits in the register map are not transferred
to their internal destinations until assertion of an I/O update,
which is not included in the timing diagrams that follow.
MSB/LSB TRANSFERS
The AD9957 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. This
functionality is controlled by Bit 0 in Control Function Register 1
(0x00). The default format is MSB first. If LSB first is active,
all data, including the instruction byte, must follow LSB-first
convention. Note that the highest number found in the bit range
column for each register is the MSB and the lowest number is
the LSB for that register (see the Register Map and Bit
Descriptions section and Table 13).
06384-
037
I7
SDIO
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
SCLK
CS
I6
I5
I4
I3
I2
I1
I0
D7
D6
D5
D4
D3
D2
D1
D0
Figure 60. Serial Port Write Timing—Clock Stall Low
06384-
038
DO7
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
DON'T CARE
I7
I6
I5
I4
I3
I2
I1
I0
SDIO
SCLK
CS
SDO
DO6
DO5
DO4
DO3
DO2
DO1
DO0
Figure 61. 3-Wire Serial Port Read Timing—Clock Stall Low
06384-
039
I7
SDIO
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
SCLK
CS
I6
I5
I4
I3
I2
I1
I0
D7
D6
D5
D4
D3
D2
D1
D0
Figure 62. Serial Port Write Timing—Clock Stall High
06384-
040
I7
SDIO
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
SCLK
CS
I6
I5
I4
I3
I2
I1
I0
DO7
DO6 DO5 DO4 DO3 DO2
DO1 DO0
Figure 63. 2-Wire Serial Port Read Timing—Clock Stall High
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