參數(shù)資料
型號(hào)： AD9957BSVZ
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 38/64頁(yè)
文件大?。?/td> 0K
描述： IC DDS 1GSPS 14BIT IQ 100TQFP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝： 1
分辨率（位）： 14 b
主 fclk： 1GHz
調(diào)節(jié)字寬（位）： 32 b
電源電壓： 1.8V, 3.3V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 托盤(pán)
產(chǎn)品目錄頁(yè)面： 552 (CN2011-ZH PDF)
配用： AD9957/PCBZ-ND - BOARD EVAL AD9957 QUADRATURE MOD
Data Sheet
AD9957
Rev. C | Page 43 of 64
The validation result latch is in a reset state whenever the sync
receiver is disabled, which forces the SYNC_SMP_ERR pin to a
Logic 0 state. To reset the validation result latch when the sync
receiver is active, however, requires the use of the Sync Timing
Validation Disable bit in the multichip sync register. To make a
setup/hold validation measurement is a two-step process. First,
write a Logic 1 to the sync timing validation disable bit. Then,
to make a measurement, write a Logic 0. The first action resets
the validation result latch and holds it in a reset state; the
second action releases the reset state and enables the validation
result latch to capture a setup/hold validation measurement.
Each time a new setup/hold validation check is desired, this
two-step procedure must be performed.
Because the programmed value of the sync validation delay
establishes the time window for a setup/hold measurement,
the amount of delay is an important consideration for proper
operation of the validation block. The value chosen should
represent a small fraction of the SYSCLK period. For example,
if the SYSCLK frequency is 1 GHz (1000 ps period), then a
reasonable sync validation delay value is 4 (~300 ps). This
allows the validation block to ensure that the local SYSCLK
and the delayed SYNC_IN edges exhibit at least 300 ps of
timing separation. Choosing too large a value can cause the
validation block to indicate a setup/hold violation when one
does not exist. Choosing too small a value can cause the
validation block to miss a setup/hold violation when one
actually exists.
SYNC
PULSE
SYSCLK
DELAY
CHE
CK
L
O
G
IC
4
SYNC VALIDATION
DELAY
SYNC_SMP_ERR
SYNC RECEIVER
SYNC TIMING VALIDATION DISABLE
SETUP
VALIDATION
HOLD
VALIDATION
12
SETUP AND HOLD VALIDATION
TO
CLOCK
GENERATION
LOGIC
FROM
SYNC
RECEIVER
DELAY
LOGIC
D Q
DELAY
RISING EDGE
DETECTOR
AND STROBE
GENERATOR
06384-
036
4
Figure 58. Sync Timing Validation Block
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參數(shù)描述
AD9957BSVZ-REEL 功能描述:IC DDS 1GSPS 14BIT IQ 100TQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
AD9957BSVZREEL13 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC
AD9958 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:2-Channel 500 MSPS DDS with 10-Bit DACs
AD9958 PCB 制造商:Analog Devices 功能描述:EVAL BOARD ((NS))
AD9958/PCB 制造商:Analog Devices 功能描述:Evaluation Board For 2-Channel 500 MSPS DDS With 10-Bit DACs 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:IC 10-BIT DAC DDS
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