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參數(shù)資料
| 型號(hào)： | AD9957BSVZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 39/64頁 |
| 文件大小： | 0K |
| 描述： | IC DDS 1GSPS 14BIT IQ 100TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 分辨率（位）： | 14 b |
| 主 fclk： | 1GHz |
| 調(diào)節(jié)字寬（位）： | 32 b |
| 電源電壓： | 1.8V, 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 552 (CN2011-ZH PDF) |
| 配用： | AD9957/PCBZ-ND - BOARD EVAL AD9957 QUADRATURE MOD |
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AD9957
Data Sheet
Rev. C | Page 44 of 64
SYNCHRONIZATION EXAMPLE
To accomplish the synchronization of multiple devices provide
each AD9957 with a SYNC_IN signal that is edge aligned across
all the devices. If the SYNC_IN signal is edge aligned at all devices,
and all devices have the same sync receiver delay and sync state
preset value, then they all have matching clock states (that is,
they are synchronized). Figure 59 shows this concept with three
AD9957s in synchronization. One device operates as a master
timing unit with the others synchronized to the master.
The master device must have its SYNC_IN pins included as part
of the synchronization distribution and delay equalization mecha-
nism. This ensures that the master maintains synchronous timing
with the other units.
The synchronization mechanism begins with the clock distribu-
tion and delay equalization block, which ensures that all devices
receive an edge-aligned REFCLK signal. However, even though
the REFCLK signal is edge aligned among all devices, this alone
does not guarantee that the clock state of each internal clock
generator is coordinated with the others. This is the role of the
synchronization and delay equalization block. This block accepts
the SYNC_OUT signal generated by the master device and
redistributes it to the SYNC_IN input of the slave units (as well
as feeding it back to the master). The goal of the redistributed
SYNC_OUT signal from the master device is to deliver an edge-
aligned SYNC_IN signal to all of the sync receivers.
Assuming that all devices share the same REFCLK edge timing
(due to the clock distribution and delay equalization block) and
that all devices share the same SYNC_IN edge timing (due to
the synchronization and delay equalization block), then all
devices should be generating an internal sync pulse in unison
(assuming all have the same value for the sync receiver delay).
With the further stipulation that all devices have the same sync
state preset value, then the synchronized sync pulses cause all of
the devices to assume the same predefined clock state simultane-
ously. That is, all devices have their internal clocks fully
synchronized.
CLOCK
SOURCE
SYNC
IN
SYNC
OUT
REF_CLK
AD9957
NUMBER 1
MASTER DEVICE
FPGA
DATA
FPGA
DATA
FPGA
DATA
EDGE
ALIGNED
AT REF_CLK
INPUTS
EDGE
ALIGNED
AT SYNC_IN
INPUTS.
P
DCL
K
SYNC
IN
SYNC
OUT
REF_CLK
AD9957
NUMBER 2
P
DCL
K
SYNC
IN
SYNC
OUT
REF_CLK
AD9957
NUMBER 3
P
DCL
K
(FOR EXAMPLE, AD951x)
CLOCK DISTRIBUTION
AND
DELAY EQUALIZATION
SYNCHRONIZATION
DISTRIBUTION AND
DELAY EQUALIZATION
(FOR EXAMPLE AD951x)
06384-
035
Figure 59. Multichip Synchronization Example
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| AD9957BSVZ-REEL | 功能描述:IC DDS 1GSPS 14BIT IQ 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9957BSVZREEL13 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC |
| AD9958 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2-Channel 500 MSPS DDS with 10-Bit DACs |
| AD9958 PCB | 制造商:Analog Devices 功能描述:EVAL BOARD ((NS)) |
| AD9958/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For 2-Channel 500 MSPS DDS With 10-Bit DACs 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:IC 10-BIT DAC DDS |
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