參數(shù)資料
型號(hào)： AD9874ABSTZ
廠商： ANALOG DEVICES INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： SPECIALTY TELECOM CIRCUIT, PQFP48
封裝： PLASTIC, MS-026BBC, LQFP-48
文件頁數(shù)： 40/40頁
文件大?。?/td> 1682K
代理商： AD9874ABSTZ
REV. A
AD9874
–9–
IFIN CLIP POINT – dBm
PERCENT
A
GE
–
%
100
80
60
40
20
0
–19.4 –19.2 –19.0 –18.8 –18.6 –18.4
+25 C
+85 C
–40 C
TPC 4a. CDF of Maximum VGA
Attenuation Clip Point (VDDx = 3.0 V,
High Bias2)
IFIN CLIP POINT – dBm
PERCENT
A
GE
–
%
100
80
60
40
20
0
–31.6
+25 C
+85 C
–40 C
–31.4 –31.2 –31.0 –30.8 –30.6 –30.4
TPC 5a. CDF of Minimum VGA
Attenuation Clip Point (VDDx = 3.0 V,
High Bias2)
SUPPLY CURRENT – mA
PERCENT
A
GE
–
%
100
80
60
40
20
0
18.5 19.0 19.5 20.0 20.5 21.0 21.5 22.0
+85 C
+25 C
–40 C
TPC 6a. CDF of Supply Current
(VDDx = 3.0 V, High Bias2)
VDDx – V
INPUT
CLIP
POINT
–
dBm
2.7
3.0
3.3
3.6
–20.5
–20.0
–19.5
–19.0
–18.5
–18.0
–17.5
+25 C
+85 C
–40 C
TPC 4b. Maximum VGA Attenuation
Clip Point vs. Supply (High Bias2)
VDDx – V
INPUT
CLIP
POINT
–
dBm
–29.5
2.7
3.0
3.3
3.6
+85 C
+25 C
–30.0
–30.5
–31.0
–31.5
–32.0
–40 C
TPC 5b. Minimium VGA Attenuation
Clip Point vs. Supply (High Bias2)
fCLK – MHz
SUPPL
Y
CURRENT
–
mA
16
13
14
10
6
2
0
12
8
4
15
17
19
21
23
25
DIGITAL
(IDDD, IDDC, AND IDDL)
DIGITAL INTERFACE
(IDDH)
ANALOG
(IDDA, IDDF, AND IDDI)
TPC 6b. Supply Current vs. fCLK
(VDDx = 3.0 V, High Bias2)
VDDx – V
INPUT
CLIP
POINT
–
dBm
–17.5
2.7
3.0
3.3
3.6
–40 C
+85 C
+25 C
–18.0
–18.5
–19.0
–19.5
–20.0
–20.5
TPC 4c. Maximum VGA Attenuation
Clip Point vs. Supply (Low Bias3)
VDDx – V
INPUT
CLIP
POINT
–
dBm
–29.5
2.7
3.0
3.3
3.6
+85 C
+25 C
–30.0
–30.5
–31.0
–31.5
–32.0
–40 C
TPC 5c. Minimium VGA Attenuation
Clip Point vs. Supply (Low Bias3)
VDDx – V
SUPPL
Y
CURRENT
–
mA
18
2.7
3.0
3.3
3.6
16
12
8
4
0
DIGITAL INTERFACE
(IDDH)
DIGITAL
(IDDD, IDDC, AND IDDL)
ANALOG
(IDDA, IDDF, AND IDDI)
14
10
6
2
TPC 6c. Supply Current vs. Supply
(High Bias2)
(VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = VDDx, VDDQ = VDDP = 5.0 V,
fCLK = 18 MSPS, fIF = 109.56 MHz, fLO = 107.4 MHz,
TA = 25 C, LO = –5 dBm, LO and CLK Synthesizer Disabled, 16-Bit Data with AGC and DVGA enabled, unless otherwise noted.)
1
1Data taken with Toko FSLM series 10
H inductors.
2High Bias corresponds to LNA_Mixer Setting of 33 in SPI Register 0x01.
3Low Bias corresponds to LNA_Mixer Setting of 12 in SPI Register 0x01.
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