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參數(shù)資料
| 型號： | AD9874ABSTZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, MS-026BBC, LQFP-48 |
| 文件頁數(shù)： | 10/40頁 |
| 文件大?。?/td> | 1682K |
| 代理商： | AD9874ABSTZ |
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REV. A
AD9874
–18–
The AD9874 also provides the means for controlling the
switching characteristics of the digital output signals via the
DS (drive strength) field of the SSICRB. This feature is useful
in limiting switching transients and noise from the digital out-
put that may ultimately couple back into the analog signal path,
potentially degrading the AD9874’s sensitivity performance.
Figures 3c and 3d show how the NF can vary as a function of
the SSI setting for an IF frequency of 109.65 MHz. The follow-
ing two observations can be made from these figures:
The NF becomes more sensitive to the SSI output drive
strength level at higher signal bandwidth settings.
The NF is dependent on the number of bits within an SSI
frame, becoming more sensitive to the SSI output drive
strength level as the number of bits is increased. As a result,
one should select the lowest possible SSI drive strength set-
ting that still meets the SSI timing requirements.
SSI OUTPUT DRIVE STRENGTH SETTING
2
10.0
4
NOISE
FIGURE
–
dB
9.6
3
1
8.0
7
6
5
24-BIT I/O DATA
9.8
9.4
9.2
9.0
8.6
8.8
8.4
8.2
16-BIT I/O DATA
w/DVGA ENABLED
16-BIT I/O DATA
Figure 3c. NF vs. SSI Output Drive Strength
(VDDx = 3.0 V, fCLK = 18 MSPS, BW = 10 kHz)
SSI OUTPUT DRIVE STRENGTH SETTING
2
14
4
NOISE
FIGURE
–
dB
12
3
1
7
6
5
24-BIT I/O DATA
13
11
9
10
8
16-BIT I/O DATA
w/DVGA ENABLED
16-BIT I/O DATA
Figure 3d. NF vs. SSI Output Drive Strength
(VDDx = 3.0 V, fCLK = 18 MSPS, BW = 75 kHz)
Table V lists the typical output rise/fall times as a function of
DS for a 10 pF load. Rise/fall times for other capacitor loads
can be determined by multiplying the typical values presented
in Table V by a scaling factor equal to the desired capacitive
load divided by 10 pF.
Table V. Typical Rise/Fall Times ( 25%) with
a 10 pF Capacitive Load for Each DS Setting
DS
Typ (ns)
013.5
1
7.2
2
5.0
3
3.7
4
3.2
5
2.8
6
2.3
7
2.0
Synchronization Using SYNCB
Many applications require the ability to synchronize one or more
AD9874 in a way that causes the output data to be precisely
aligned to an external asynchronous signal. For example, receiver
applications employing diversity often require synchronization of
multiple AD9874 digital outputs. Satellite communication appli-
cations using TDMA methods may require synchronization
between payload bursts to compensate for reference frequency
drift and Doppler effects.
SYNCB can be used for this purpose. It is an active-low signal
that clears the clock counters in both the decimation filter and
the SSI port. The counters in the clock synthesizers are not
reset because it is presumed that the CLK signals of multiple
chips would be connected. SYNCB also resets the modulator,
resulting in a large-scale impulse that must propagate through
the AD9874’s digital filter and SSI data formatting circuitry
before recovering valid output data. At a result, data samples
unaffected by this SYNCB induced impulse can be recovered
12 output data samples after SYNCB goes high (independent of
the decimation factor).
Figure 4a shows the timing relationship between SYNCB and
the SSI port’s CLKOUT and FS signals. SYNCB is an asyn-
chronous active-low signal that must remain low for at least half
an input clock period (i.e., 1/(2
fCLK)). CLKOUT remains
high while FS remains low upon SYNCB going low. CLKOUT
will become active within one to two output clock periods upon
SYNCB returning high. FS will reappear several output cycles
later, depending on the digital filter’s decimation factor and the
SSIORD setting. Note that for any decimation factor and
SSIORD setting, this delay is fixed and repeatable. To verify
proper synchronization, the FS signals of the multiple AD9874
devices should be monitored.
FS
SYNCB
CLKOUT
Figure 4a. SYNCB Timing
Interfacing to DSPs
The AD9874 connects directly to an Analog Devices programmable
digital signal processor (DSP). Figure 4b illustrates an example
with the Blackfin
series of ADSP-2153x processors. The Blackfin
DSP series is a family of 16-bit products optimized for telecommu-
nications applications with its dynamic power management feature,
making it well suited for portable radio products. The code
compatible family members share the fundamental core attributes
of high performance, low power consumption, and the ease-of-use
advantages of a microcontroller instruction set.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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