- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄298813 > AD9874ABSTZ (ANALOG DEVICES INC) SPECIALTY TELECOM CIRCUIT, PQFP48 PDF資料下載
參數(shù)資料
| 型號(hào)： | AD9874ABSTZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, MS-026BBC, LQFP-48 |
| 文件頁數(shù)： | 26/40頁 |
| 文件大?。?/td> | 1682K |
| 代理商： | AD9874ABSTZ |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當(dāng)前第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁
REV. A
AD9874
–32–
Figure 22b plots the nominal system NF with 16-bit output
data as a function of AGC in both narrow-band and wideband
mode. In wideband mode, the NF curve is virtually unchanged
relative to the 24-bit output data because the output SNR
before truncation is always less than the 96 dB SNR that 16-bit
data can support.
However, in narrow-band mode, where the output SNR
approaches or exceeds the SNR that can be supported with 16-bit
data, the degradation in system NF is more severe. Further-
more, if the signal processing within the DSP adds noise at the
level of an LSB, the system noise figure can be degraded even
more than Figure 22b shows. For example, this could occur in a
fixed 16-bit DSP whose code is not optimized to process the
AD9874’s 16-bit data with minimal quantization effects. To
limit the quantization effects within the AD9874, the 24-bit
data undergoes noise shaping just prior to 16-bit truncation,
thus reducing the in-band quantization noise by 5 dB (with 23
oversampling). This explains why 98.8 dBFS SNR performance
is still achievable with 16-bit data in a 10 kHz BW.
NOISE
FIGURE
–
dB
15
8
14
13
12
11
10
9
SNR = 98.8dBFS
BW = 50kHz
BW = 150kHz
SNR = 83dBFS
SNR = 94.1dBFS
BW = 10kHz
SNR = 89.9dBFS
16
17
3
6
0
9
12
VGA ATTENUATION – dB
Figure 22b. Nominal System Noise Figure and Peak SNR
vs. AGCG Setting (fIF = 73.35 MHz, fCLK = 18 MSPS, and
16-bit I/Q data)
APPLICATION CONSIDERATIONS
Frequency Planning
The LO frequency (and/or ADC clock frequency) must be
chosen carefully to prevent known internally generated spurs
from mixing down along with the desired signal, thus degrad-
ing the SNR performance. The major sources of spurs in the
AD9874 are the ADC clock and digital circuitry operating at
1/3 of fCLK. Thus, the clock frequency (fCLK) is the most
important variable in determining which LO (and therefore
IF) frequencies are viable.
Many applications have frequency plans that take advantage of
industry-standard IF frequencies due to the large selection of
low cost crystal or SAW filters. If the selected IF frequency and
ADC clock rate result in a problematic spurious component, an
alternative ADC clock rate should be selected by slightly modi-
fying the decimation factor and CLK synthesizer settings (if
used) such that the output sample rate remains the same. Also,
applications requiring a certain degree of tuning range should
take into consideration the location and magnitude of these
spurs when determining the tuning range as well as optimum IF
and ADC clock frequency.
Figure 23a plots the measured in-band noise power as a func-
tion of the LO frequency for fCLK = 18 MHz and an output
signal bandwidth of 150 kHz when no signal is present. Any LO
frequency resulting in large spurs should be avoided. As this
figure shows, large spurs result when the LO is fCLK/8 = 2.25 MHz
away from a harmonic of 18 MHz (i.e., n fCLK
fCLK/8). Also
problematic are LO frequencies whose odd order harmonics
(i.e., m fLO) mix with harmonics of fCLK to fCLK/8. This spur
mechanism is a result of the mixer being internally driven by a
squared-up version of the LO input consisting of the LO fre-
quency and its odd order harmonics. These spur frequencies
can be calculated from the relation
mf
n
f
LO
CLK
=±
()
18
(12)
where m = 1, 3, 5... and n = 1, 2, 3...
A second source of spurs is a large block of digital circuitry that
is clocked at fCLK/3. Problematic LO frequencies associated with
this spur source are given by:
ff
n f
f
LO
CLK
=+
±
/3
8
(13)
where n = 1, 2, 3 ...
IN-B
AND
PO
WER
–
dBFS
–60
–70
–80
–90
–50
0
250
300
200
150
100
50
LO FREQUENCY – MHz
Figure 23a. Total In-Band Noise + Spur Power with No Signal Applied as a Function of the LO Frequency
(fCLK = 18 MHz and Output Signal Bandwidth of 150 kHz)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9874ABSTZRL | SPECIALTY TELECOM CIRCUIT, PQFP48 |
| ADC0831CIWM | 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO14 |
| ADE7116ASTZF8-RL | SPECIALTY ANALOG CIRCUIT, PQFP64 |
| ADE7753ARSZRL | SPECIALTY ANALOG CIRCUIT, PDSO20 |
| ADEX-R10+ | 10 MHz - 1000 MHz RF/MICROWAVE DOUBLE BALANCED MIXER, 8.3 dB CONVERSION LOSS-MAX |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9874BST | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| AD9874EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Digitizing Subsystem |
| AD9874-EB | 制造商:Analog Devices 功能描述: |
| AD9874-EBZ | 功能描述:BOARD EVAL FOR AD9874 制造商:analog devices inc. 系列:- 零件狀態(tài):有效 類型:數(shù)字轉(zhuǎn)換器 頻率:10MHz ~ 300MHz 配套使用產(chǎn)品/相關(guān)產(chǎn)品:AD9874 所含物品:板 標(biāo)準(zhǔn)包裝:1 |
| AD9875 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。