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參數(shù)資料
| 型號： | AD9874ABSTZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, MS-026BBC, LQFP-48 |
| 文件頁數(shù)： | 16/40頁 |
| 文件大小： | 1682K |
| 代理商： | AD9874ABSTZ |
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REV. A
AD9874
–23–
The mixer’s differential LO port is driven by the LO buffer
stage shown in Figure 6, which can be driven single-ended or
differential. Since it is self-biasing, the LO signal level can be
ac-coupled and range from 0.3 V p-p to 1.0 V p-p with negligible
effect on performance. The mixer’s open-collector outputs,
MXOP and MXON, drive an external resonant tank consisting
of a differential LC network tuned to the IF of the band-pass
-
ADC (i.e., fIF2_ADC = fCLK/8). The two inductors provide a
dc bias path for the mixer core via a series resistor of 50
, which
is included to dampen the common-mode response. The mixer’s
output must be ac-coupled to the input of the band-pass - ADC,
IF2P, and IF2N via two 100 pF capacitors to ensure proper tuning
of the LC center frequency.
The external differential LC tank forms the resonant element
for the first resonator of the band-pass -
modulator, and so
must be tuned to the fCLK/8 center frequency of the modulator.
The inductors should be chosen such that their impedance at
fCLK/8 is about 140
(i.e., L = 180/f
CLK). An accuracy of 20%
is considered to be adequate. For example, at fCLK = 18 MHz,
L = 10
H is a good choice. Once the inductors have been
selected, the required tank capacitance may be calculated using
the relation fCLK/8 = 1/{2
(2L
C)
1/2}.
For example, at fCLK = 18 MHz and L = 10
H, a capacitance of
250 pF is needed. However, in order to accommodate an induc-
tor tolerance of
10%, the tank capacitance must be adjustable
from 227 pF to 278 pF. Selecting an external capacitor of
180 pF ensures that even with a 10% tolerance and stray capaci-
tances as high as 30 pF, the total capacitance will be less than
the minimum value needed by the tank. Extra capacitance is
supplied by the AD9874’s on-chip programmable capacitor
array. Since the programming range of the capacitor array is at
least 160 pF, the AD9874 has plenty of range to make up for
the tolerances of low cost external components. Note that if fCLK
is increased by a factor of 1.44 MHz to 26 MHz so that fCLK/8
becomes 3.25 MHz, reducing L and C by approximately the
same factor (i.e., L = 6.9
H and C = 120 pF) still satisfies the
requirements stated above.
The selection of the inductors is an important consideration in
realizing the full linearity performance of the AD9874. This is
true when operating the LNA and mixer at maximum bias and
low clock frequency. Figure 10 shows how the two-tone input-
referred IMD versus the input level performance at an IF of
109 MHz and fCLK of 18 MHz varies between Toko’s FSLM
series and Coilcraft’s 1812CS series inductors. The graph also
shows the extrapolated point of intersection used to determine
the IIP3 performance. Note that the Coilcraft inductor provides
a 7 dB to 8 dB improvement in performance and closely
approximates the 3:1 slope associated with a third order
linearity compared to the 2.65:1 slope associated with the
Toko inductor. The Coilcraft 1008CS series showed perfor-
mance similar to that of the 1812CS series. It is worth noting
that the difference in IMD performance between these two
inductor families with an fCLK of 26 MHz is insignificant.
–30
–24
–18
–36
–48
–42
–54
0
–20
–40
–60
–80
–100
–120
–140
INPUT
REFERRED
PO
WER
–
dBm
TOKO INDUCTOR
PIMD = 2.64
PIN + 4.6
PIN
fIN = 109.65MHz
COILCRAFT
PIMD = 2.92
PIN + 6.9
Figure 10. IMD Performance between Different Inductors
with LNA and Mixer at Full Bias and fCLK of 18 MHz
Both the LNA and mixer have four programmable bias settings so
that current consumption can be minimized for a given application.
Figures 11a, 11b, and 11c show how the LNA and mixer’s noise
figure (NF), linearity (IIP3), IF clip point, current consumption,
and frequency response are affected for a given LNA/mixer bias
setting. The measurements were taken at an IF = 73.35 MHz and
LO = 71.1 MHz, with supplies set to 3 V.
1_0
13
12
11
10
9
8
NOISE
FIGURE
–
dB
1_1
1_2
1_3
2_0
2_1
2_2
2_3
3_0
3_1
3_2
3_3
–20
–18
–16
–14
–12
–10
CLIP
POINT
–
dBm
CLIP POINT
NOISE FIGURE
LNA_MIXER BIAS SETTING
Figure 11a. LNA/Mixer Noise Figure and
Conversion Gain vs. Bias Setting
1_0
5
0
–5
–10
–15
–25
INPUT
IIP3
–
dBm
1_1
1_2 1_3
2_0 2_1
2_2
2_3 3_0
3_1 3_2
3_3
7.00
8.25
5.75
4.50
3.25
2.00
IDDI
–
mA
9.50
–20
LNA_MIXER CURRENT
IIP3
LNA_MIXER BIAS SETTING
Figure 11b. LNA/Mixer IIP3 and Current
Consumption vs. Bias Setting
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9874BST | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| AD9874EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Digitizing Subsystem |
| AD9874-EB | 制造商:Analog Devices 功能描述: |
| AD9874-EBZ | 功能描述:BOARD EVAL FOR AD9874 制造商:analog devices inc. 系列:- 零件狀態(tài):有效 類型:數(shù)字轉換器 頻率:10MHz ~ 300MHz 配套使用產(chǎn)品/相關產(chǎn)品:AD9874 所含物品:板 標準包裝:1 |
| AD9875 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
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