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參數(shù)資料
| 型號(hào)： | AD9874ABSTZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, MS-026BBC, LQFP-48 |
| 文件頁數(shù)： | 19/40頁 |
| 文件大?。?/td> | 1682K |
| 代理商： | AD9874ABSTZ |
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REV. A
AD9874
–26–
Once the AD9874 has been tuned, the noise figure degradation
attributed solely to the temperature drift of the LC and RC
resonators is minimal. Since the drift of the RC resonator is
actually negligible compared to that of the LC resonator, the
external L and C components’ temperature drift characteristics
tend to dominate. Figure 13d shows the degradation in noise
figure as the product of the LC value is allowed to vary from
–12.5% to +12.5%. Note that the noise figure remains relatively
constant over a
3.5% range (i.e.,
35,000 ppm), suggesting
that most applications will not be required to retune over the
operating temperature range.
–15
12
11
NF
–
dB
10
LC ERROR – %
9
8
05
10
15
–5
–10
BW = 75kHz
BW = 10kHz
BW = 30kHz
Figure 13d. Typical Noise Figure Degradation
from L and C Component Drift (fCLK = 18 MSPS,
fIF = 73.3501 MHz)
DECIMATION FILTER
The decimation filter shown in Figure 14 consists of an fCLK/8
complex mixer and a cascade of three linear phase FIR filters:
DEC1, DEC2, and DEC3. DEC1 downsamples by a factor of
12 using a fourth order comb filter. DEC2 also uses a fourth
order comb filter, but its decimation factor is set by the M field
of Register 0x07. DEC3 is either a decimate-by-5 FIR filter or a
decimate-by-4 FIR filter, depending on the value of the K bit
within Register 0x07. Thus, the composite decimation factor
can be set to either 60
M or 48
M for K equal to 0 or 1,
respectively.
The output data rate (fOUT) is equal to the modulator clock
frequency (fCLK) divided by the digital filter’s decimation factor.
Due to the transition region associated with the decimation
filter’s frequency response, the decimation factor must be
selected such that fOUT is equal to or greater than twice the
signal bandwidth. This ensures low amplitude ripple in the pass
band along with the ability to provide further application-spe-
cific digital filtering prior to demodulation.
4
OR
5
COS
SIN
DATA
FROM
-
MODULATOR
DEC1
SINC4
FILTER
12
DEC2
SINC4
FILTER
M + 1
M
DEC3
FIR
FILTER
K
I
Q
COMPLEX
DATA TO
SSI PORT
Figure 14. Decimation Filter Architecture
Figure 15a shows the response of the decimation filter at a
decimation factor of 900 (K = 0, M = 14) and a sampling
clock frequency of 18 MHz. In this example, the output data
rate (fOUT) is 20 kSPS, with a usable complex signal band-
width of 10 kHz centered around dc. As this figure shows,
the first and second alias bands (occurring at even integer
multiples of fOUT/2) have the least attenuation but provide at
least 88 dB of attenuation. Note that signals falling around
frequency offsets that are odd integer multiples of fOUT/2
(i.e., 10 kHz, 30 kHz, and 50 kHz) will fall back into the
transition band of the digital filter.
FREQUENCY – kHz
0
–40
–100
030
10
20
–20
–60
–80
40
100
dB
FOLD-
ING
POINT
5.0kHz PASS BAND
–120
70
80
60
50
90
–88dB
–101dB
–103dB
Figure 15a. Decimation Filter Frequency Response
for fOUT = 20 kSPS (fCLK = 18 MHz, OSR = 900)
Figure 15b shows the response of the decimation filter with a
decimation factor of 48 and a sampling clock rate of 26 MHz. The
alias attenuation is at least 94 dB and occurs for frequencies at the
edges of the fourth alias band. The difference between the alias
attenuation characteristics of Figure 15b and those of Figure 15a is
due to the fact that the third decimation stage decimates by a factor
of 5 for Figure 15a compared with a factor of 4 for Figure 15b.
0
–40
–100
–20
–60
–80
dB
–120
FREQUENCY – MHz
0
1.5
0.5
1.0
2.0
2.5
135.466kHz PASS BAND
–98dB
–115dB
–94dB
Figure 15b. Decimation Filter Frequency Response
for fOUT = 541.666 kSPS (fCLK = 26 MHz, OSR = 48)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9874BST | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| AD9874EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Digitizing Subsystem |
| AD9874-EB | 制造商:Analog Devices 功能描述: |
| AD9874-EBZ | 功能描述:BOARD EVAL FOR AD9874 制造商:analog devices inc. 系列:- 零件狀態(tài):有效 類型:數(shù)字轉(zhuǎn)換器 頻率:10MHz ~ 300MHz 配套使用產(chǎn)品/相關(guān)產(chǎn)品:AD9874 所含物品:板 標(biāo)準(zhǔn)包裝:1 |
| AD9875 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
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