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參數(shù)資料
| 型號： | AD9874ABSTZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, MS-026BBC, LQFP-48 |
| 文件頁數(shù)： | 30/40頁 |
| 文件大?。?/td> | 1682K |
| 代理商： | AD9874ABSTZ |
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REV. A
AD9874
–36–
and digital driver strength should be set to their lowest pos-
sible settings to minimize the potential harmful effects of
digital induced noise while preserving a reliable data link to
the DSP. Note that the SSICRA, SSICRB, and SSIORD
registers (i.e., 0x18, 0x19, and 0x1A) provide a large degree
of flexibility for optimization of the SSI interface.
Synchronization of Multiple AD9874s
Some applications such as receiver diversity and beam steering
may require two or more AD9874s operating in parallel while
maintaining synchronization. Figure 28 shows an example of
how multiple AD9874s can be cascaded, with one device serv-
ing as the master and the other devices serving as the slaves. In
this example, all of the devices have the same SPI register con-
figuration since they share the same SPI interface to the DSP.
Since the state of each of the AD9874’s internal counters is
unknown upon initialization, synchronization of the devices is
required via a SYNCB pulse (see Figure 4) to synchronize their
digital filters and ensure precise time alignment of the data
streams.
Although all of the devices’ synthesizers are enabled, the LO
and CLK signals for the slaves(s) are derived from the masters’
synthesizers and are referenced to an external crystal oscillator.
All of the necessary external components (i.e., loop filters,
varactor, LC, and VCO) required to ensure proper closed-loop
operation of these synthesizers are included.
Note that although the VCO output of the LO synthesizer is
ac-coupled to the slave’s LO input(s), all of the CLK inputs of
the devices must be dc-coupled if the AD9874’s CLK oscillators
are enabled. This is due to the dc current required by the CLK
oscillators in each device. In essence, these negative impedance
cores are operating in parallel, increasing the effective Q of the
LC resonator circuit. Note that RBIAS should be sized such
that the sum of the oscillators’ dc bias currents maintains a
common-mode voltage of around 1.6 V.
VCO
25
23
24
PE
PC
PD
33
SYNCB
31
FS
29
28
DOUTA
CLKOUT
35
fREF
19
20
CLKP
CLKN
LOP
LON
43
42
IFIN
47
15
AD9874
MASTER
IOUTC
LOOP
FILTER
38
15
IOUTC
25
23
24
PE
PC
PD
35
LOP
LON
43
42
IFIN
47
31
FS
29
28
DOUTA
CLKOUT
33
SYNCB
TO
DSP
CLKP
CLKN
IOUTL
TO DSP
FROM
DSP
LOOP
FILTER
CVAR
RD
RF
CP
CZ
0.1 F
LOSC
RBIAS
COSC
TO OTHER
AD9874s
FROM
CRYSTAL
OSCILLATION
VDDC
TO OTHER
AD9874s
AD9874
SLAVE
19
20
fREF
Figure 28. Example of Synchronizing Multiple AD9874s
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9874BST | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| AD9874EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Digitizing Subsystem |
| AD9874-EB | 制造商:Analog Devices 功能描述: |
| AD9874-EBZ | 功能描述:BOARD EVAL FOR AD9874 制造商:analog devices inc. 系列:- 零件狀態(tài):有效 類型:數(shù)字轉(zhuǎn)換器 頻率:10MHz ~ 300MHz 配套使用產(chǎn)品/相關(guān)產(chǎn)品:AD9874 所含物品:板 標(biāo)準(zhǔn)包裝:1 |
| AD9875 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
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