參數(shù)資料
型號(hào)： AD9874ABSTZ
廠商： ANALOG DEVICES INC
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： SPECIALTY TELECOM CIRCUIT, PQFP48
封裝： PLASTIC, MS-026BBC, LQFP-48
文件頁(yè)數(shù)： 2/40頁(yè)
文件大?。?/td> 1682K
代理商： AD9874ABSTZ
REV. A
AD9874
–10–
LO DRIVE – dBm
GAIN
V
ARIA
TION
–
dB
0.1
–20
–14
–8
–5
0
–0.2
–0.4
–0.6
–0.8
–0.1
–0.3
–0.5
–0.7
–11
–17
LOW BIAS
HIGH BIAS
TPC 7a. Normalized Gain Variation
vs. LO Drive (VDDx = 3.0 V)
FREQUENCY – kHz
dBFS
0
–140
–20
–40
–60
–80
–100
–120
–80
–60
–40
–20
0
20
40
60
80
–2.8dBFS OUTPUT
NBW = 3.66kHz
fCLK = 18MHz
MAX VGA ATTEN
DEC–BY–120
TPC 8a. Complex FFT of Baseband
I/Q for Single-Tone (High Bias)
FREQUENCY – kHz
dBFS
0
–140
–20
–40
–60
–80
–100
–120
–80
–60
–40
–20
0
20
40
60
80
NBW = 3.66kHz
fCLK = 18MHz
MAX VGA ATTEN
DEC–BY–120
IMD = 74dBc
–18.2dBFS OUTPUT
TPC 9a. Complex FFT of Baseband
I/Q for Dual Tone IMD (High Bias
with Each IFIN Tone @ –35 dBm)
LO DRIVE – dBm
NOISE
FIGURE
–
dBc
9.0
–20
–10
0
5
8.6
8.2
7.8
7.4
7.0
8.4
8.0
7.6
7.2
–5
–15
NF-HIGH BIAS
IMD-HIGH BIAS
NF-LOW BIAS
IMD-LOW BIAS
8.8
IMD
w/
IFIN
=
–36
dBm
–
dBc
0
–20
–40
–60
–80
–30
–50
–70
–10
TPC 7b. Noise Figure and IMD
vs. LO Drive (VDDx = 3.0 V)
IFIN – dBm
dBFS
0
–30
–14
ADC GOES INTO
HARD COMPRESSION
–28
–26
–24
–22
–20
–18
–16
–2
–4
–6
–8
–10
–12
2.7V
3.0V
3.3V
3.6V
TPC 8b. Gain Compression vs. IFIN
(High Bias2)
IFIN – dBm
IMD
–
dBc
–70
–124
–76
–82
–88
–100
–106
–118
–51
–48
–45
–42
–39
–36
–33
–30
PIN
2.7V
3.6V
3.0V
3.3V
–130
–112
–94
PIN
–
dBFS
–15
–42
–18
–21
–24
–30
–33
–39
–45
–36
–27
TPC 9b. IMD vs. IFIN (High Bias2)
IFIN – dBm
dBm
–12
–36
–18
–24
–30
–36
–15
–21
–27
–33
–30
–24
–18
–12
–6
0
HIGH BIAS
LOW BIAS
TPC 7c. Gain Compression vs. IFIN
with 16 dB LNA Attenuator Enabled
IFIN – dBm
dBFS
0
–30
–14
ADC DOES NOT GO INTO
HARD COMPRESSION
–28
–26
–24
–22
–20
–18
–14
–2
–4
–6
–8
–10
–12
2.7V
3.0V
3.3V
3.6V
–16
TPC 8c. Gain Compression vs. IFIN
(Low Bias3)
IFIN – dBm
IMD
–
dBc
–55
–109
–61
–67
–73
–85
–91
–103
–51
–48
–45
–42
–39
–36
–33
–30
PIN
2.7V
3.6V
3.0V
3.3V
–115
–97
–79
PIN
–
dBFS
–15
–42
–18
–21
–24
–30
–33
–39
–45
–36
–27
TPC 9c. IMD vs. IFIN (Low Bias3)
(VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = VDDx, VDDQ = VDDP = 5.0 V,
fCLK = 18 MSPS, fIF = 109.56 MHz, fLO = 107.4 MHz,
TA = 25 C, LO = –5 dBm, LO and CLK Synthesizer Disabled, 16-Bit Data with AGC and DVGA enabled, unless otherwise noted.)
1
1Data taken with Toko FSLM series 10
H inductors.
2High Bias corresponds to LNA_Mixer Setting of 33 in SPI Register 0x01.
3Low Bias corresponds to LNA_Mixer Setting of 12 in SPI Register 0x01.
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