參數(shù)資料
型號(hào): AD9874ABSTZ
廠商: ANALOG DEVICES INC
元件分類: 通信及網(wǎng)絡(luò)
英文描述: SPECIALTY TELECOM CIRCUIT, PQFP48
封裝: PLASTIC, MS-026BBC, LQFP-48
文件頁數(shù): 29/40頁
文件大?。?/td> 1682K
代理商: AD9874ABSTZ
REV. A
AD9874
–35–
This second IF signal is then digitized by the - ADC, demodu-
lated into its quadrature I and Q components, filtered via matching
decimation filters, and reformatted to enable a synchronous serial
interface to a DSP. In this example, the AD9874’s LO and CLK
synthesizers are both enabled, requiring some additional passive
components (for the synthesizer’s loop filters and CLK oscillator)
and a VCO for the LO synthesizer. Note that not all of the
required decoupling capacitors are shown. Refer to the previous
section and Figure 26 for more information on required external
passive components.
The selection of the first IF frequency is often based on the
availability of low cost standard crystal or SAW filters as well as
system frequency planning considerations. In general, crystal
filters are often used for narrow-band radios having channel
bandwidths below 50 kHz with IFs below 120 MHz, while SAW
filters are more suited for channel bandwidths greater than
50 kHz with IFs greater than 70 MHz. The ultimate stop-band
rejection required by the IF filter will depend on how much
suppression is required at the AD9874’s image band resulting
from downconversion to the second IF. This image band is
offset from the first IF by twice the second IF frequency (i.e.,
fCLK/4, depending on high or low side injection).
The selectivity and bandwidth of the IF filter will depend on
both the magnitude and frequency offset(s) of the adjacent
channel blocker(s) that could overdrive the AD9874’s input
or generate in-band intermodulation components. Further
suppression is performed within the AD9874 by its inherent
band-pass response and digital decimation filters. Note that
some applications will require additional application-specific
filtering performed in the DSP that follows the AD9874 to
remove the adjacent channel and/or implement a matched
filter for optimum signal detection.
The output data rate of the AD9874, fOUT, should be chosen
to be at least twice the bandwidth or symbol rate of the desired
signal to ensure that the decimation filters provide a flat pass-
band response as well as to allow for postprocessing by a DSP.
Once fOUT is determined, the decimation factor of the digital
filters should be set such that the input clock rate, fCLK, falls
between the AD9874’s rated operating range of 13 MHz to
26 MHz and no significant spurious products related to fCLK fall
within the desired pass band, resulting in a reduction in sensitiv-
ity performance. If a spurious component is found to limit the
sensitivity performance, the decimation factor can often be
modified slightly to find a spurious free pass band. Selecting a
higher fCLK is typically more desirable given a choice, since
the first IF’s filtering requirements often depend on the tran-
sition region between the IF frequency and the image band
(i.e.,
fCLK/4 ). Lastly, the output SSI clock rate, fCLKOUT,
RF
INPUT
PRESELECT
FILTER
TUNER
IF CRYSTAL OR
SAW FILTER
VDDA
-
ADC
LNA
VCO
ADF42xx
PLL SYN
REFIN
TO
DSP
AD9874
DECIMATION
FILTER
SAMPLE CLOCK
SYNTHESIZER
IOUTC
LOOP
FILTER
LOP
LON
VCO
LOOP
FILTER
VDDC
IOUTC
CLKP
CLKN
FROM DSP
LO
SYNTH.
VOLTAGE
REFERENCE
SPI
RREF
VREFP
VREFN
SYNCB
PC
PD
PE
CRYSTAL
OSCILLATOR
IFIN
–16dB
LNA
VXOP
VXON
II-2P
II-2N
DAC AGC
FORMATTING/SSI
DOUTA
DOUTB
FS
CLKOUT
CONTROL LOGIC
GCP
GCN
IF2 =
fCLK/8
Figure 27. Typical Dual Conversion Superheterodyne Application Using the AD9874
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