參數(shù)資料
型號(hào): AD9548BCPZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 91/112頁(yè)
文件大小: 0K
描述: IC CLOCK GEN/SYNCHRONIZR 88LFCSP
產(chǎn)品變化通告: AD9548 Mask Change 20/Oct/2010
標(biāo)準(zhǔn)包裝: 1
類型: 時(shí)鐘/頻率發(fā)生器,同步器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum
輸入: CMOS,LVDS,LVPECL
輸出: CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 是/是
頻率 - 最大: 750kHz
電源電壓: 1.71 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 88-VFQFN 裸露焊盤(pán),CSP
供應(yīng)商設(shè)備封裝: 88-LFCSP-VQ(12x12)
包裝: 托盤(pán)
AD9548
Data Sheet
Rev. E | Page 8 of 112
REFERENCE SWITCHOVER SPECIFICATIONS
Table 10.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
REFERENCE SWITCHOVER SPECIFICATIONS
Maximum Output Phase Perturbation (Phase
Build-Out Switchover)
40
200
ps
Assumes a jitter-free reference; satisfies
Telcordia GR-1244-CORE requirements
Maximum Time/Time Slope (Hitless
Switchover)
315
65,535
ns/sec
Minimum/maximum values are
programmable upper bounds; a minimum
value ensures <10% error; satisfies
Telcordia GR-1244-CORE requirements
Time Required to Switch to a New Reference
Hitless Switchover
5
sec
Calculated using the nominal phase
detector period (NPDP = R/fREF)1
Phase Build-Out Switchover
3
sec
Calculated using the nominal phase
detector period (NPDP = R/fREF)1
1
fREF is the frequency of the active reference; R is the frequency division factor determined by the R-divider.
DISTRIBUTION CLOCK OUTPUTS (OUT0 TO OUT3)
Table 11.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL MODE
Using internal current setting resistor
Maximum Output Frequency
725
MHz
Rise/Fall Time (20% to 80%)
180
315
ps
100 termination across output pins
Duty Cycle
45
55
%
Differential Output Voltage Swing
630
770
910
mV
Magnitude of voltage across pins; output
driver static
Common-Mode Output Voltage
AVDD3
1.5
AVDD3 1.3
AVDD3
1.05
V
Output driver static
LVDS MODE
Using internal current setting resistor
(nominal 3.12 k)
Maximum Output Frequency
725
MHz
Rise/Fall Time1 (20% to 80%)
200
350
ps
100 termination across the output pair
Duty Cycle
40
60
%
Differential Output Voltage Swing
Balanced, VOD
247
454
mV
Voltage swing between output pins;
output driver static
Unbalanced, ΔVOD
50
mV
Absolute difference between voltage
swing of normal pin and inverted pin;
output driver static
Offset Voltage
Common-Mode, VOS
1.125
1.375
V
Output driver static
Common-Mode Difference, ΔVOS
50
mV
Voltage difference between pins; output
driver static
Short-Circuit Output Current
13
24
mA
Output driver static
CMOS MODE
Weak drive option not supported for
operating the CMOS drivers using a 1.8 V
supply
Maximum Output Frequency
3.3 V Supply
10 pF load
Strong Drive Strength Setting
250
MHz
Weak Drive Strength Setting
25
MHz
1.8 V Supply
150
MHz
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