參數(shù)資料
型號(hào)： AD9548BCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 41/112頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK GEN/SYNCHRONIZR 88LFCSP
產(chǎn)品變化通告： AD9548 Mask Change 20/Oct/2010
標(biāo)準(zhǔn)包裝： 1
類型： 時(shí)鐘/頻率發(fā)生器，同步器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:1
差分 - 輸入:輸出： 是/是
頻率 - 最大： 750kHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 88-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 88-LFCSP-VQ（12x12）
包裝： 托盤
AD9548
Data Sheet
Rev. E | Page 34 of 112
Each coefficient has a fractional component representing a
value from 0 up to, but not including, unity. Each coefficient
also has an exponential component representing a power of 2
with a negative exponent. That is, the user enters a positive
number (x) that the hardware interprets as a negative exponent
of two (2x). Thus, the , and coefficients always represent
values less than unity. The coefficient, however, has two
additional exponential components, but the hardware interprets
these as a positive exponent of 2 (that is, 2x). This allows the
coefficient to be a value greater than unity. The positive
exponent appears as two separate terms in order to provide
sufficient dynamic range.
DPLL Phase Lock Detector
The DPLL contains an all-digital phase lock detector. The user
controls the threshold sensitivity and hysteresis of the phase
detector via the profile registers.
The phase lock detector behaves in a manner analogous to
water in a tub (see Figure 42). The total capacity of the tub is
4096 units with 2048 denoting empty, 0 denoting the 50%
point, and +2048 denoting full. The tub also has a safeguard to
prevent overflow. Furthermore, the tub has a low water mark at
1024 and a high water mark at +1024. To change the water
level, the user adds water with a fill bucket or removes water
with a drain bucket. The user specifies the size of the fill and
drain buckets via the 8-bit fill rate and drain rate values in the
profile registers.
The water level in the tub is what the lock detector uses to
determine the lock and unlock conditions. Whenever the water
level is below the low water mark (1024), the detector
indicates an unlock condition. Conversely, whenever the water
level is above the high water mark (+1024), the detector indicates
a lock condition. While the water level is between the marks,
the detector simply holds its last condition. This concept appears
graphically in Figure 42, with an overlay of an example of the
instantaneous water level (vertical) vs. time (horizontal) and the
resulting lock/unlock states.
During any given PFD phase error sample, the detector either
adds water with the fill bucket or removes water with the drain
bucket (one or the other but not both). The decision of whether
to add or remove water depends on the threshold level specified
by the user. The phase lock threshold value is a 16-bit number
stored in the profile registers and is expressed in picoseconds.
Thus, the phase lock threshold extends from 0 ns to ±65.535 ns
and represents the magnitude of the phase error at the output of
the PFD.
The phase lock detector compares each phase error sample at
the output of the PFD to the programmed phase threshold
value. If the absolute value of the phase error sample is less than
or equal to the programmed phase threshold value, then the
detector control logic dumps one fill bucket into the tub.
Otherwise, it removes one drain bucket from the tub. Notice
that it is not the polarity of the phase error sample, but its
magnitude relative to the phase threshold value, that determines
whether to fill or drain. If more filling is taking place than
draining, the water level in the tub eventually rises above the
high water mark (+1024), which causes the phase lock detector
to indicate lock. If more draining is taking place than filling,
then the water level in the tub eventually falls below the low
water mark (1024), which causes the phase lock detector to
indicate unlock. The ability to specify the threshold level, fill
rate, and drain rate enables the user to tailor the operation of
the phase lock detector to the statistics of the timing jitter
associated with the input reference signal.
0
2048
–2048
1024
–1024
LOCK LEVEL
UNLOCK LEVEL
LOCKED
UNLOCKED
PREVIOUS
STATE
FILL
RATE
DRAIN
RATE
08
02
2-
01
7
Figure 42. Lock Detector Diagram
Note that whenever the AD9548 enters the free-run or holdover
mode, the DPLL phase lock detector indicates unlocked. In
addition, whenever the AD9548 performs a reference switch-
over, the state of the lock detector prior to the switch is
preserved during the transition period.
DPLL Frequency Lock Detector
The operation of the frequency lock detector is identical to that
of the phase lock detector. The only difference is that the fill or
drain decision is based on the period deviation between the
reference and feedback signals of the DPLL instead of the phase
error at the output of the PFD.
The frequency lock detector uses a 24-bit frequency threshold
register specified in units of picoseconds. Thus, the frequency
threshold value extends from 0 μs to ±16.777215 μs. It represents
the magnitude of the difference in period between the reference
and feedback signals at the input to the DPLL. For example, if
the reference signal is 1.25 MHz and the feedback signal is 1.38
MHz, then the period difference is approximately 75.36 ns
(|1/1,250,000 1/1,380,000| ≈ 75.36 ns).
DIRECT DIGITAL SYNTHESIZER
DDS Overview
One of the primary building blocks of the digital PLL is a direct
digital synthesizer (DDS). The DDS behaves like a sinusoidal
signal generator. The frequency of the sinusoid generated by the
DDS is determined by a frequency tuning word (FTW), which
is a digital (that is, numeric) value. Unlike an analog sinusoidal
generator, a DDS uses digital building blocks and operates as a
sampled system. Thus, it requires a sampling clock (fS) that
serves as the fundamental timing source of the DDS. The
accumulator behaves as a modulo-248 counter with a
programmable step size (FTW). A block diagram of the DDS
appears in Figure 43.
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