參數(shù)資料
型號： AD9548BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 46/112頁
文件大小： 0K
描述： IC CLOCK GEN/SYNCHRONIZR 88LFCSP
產(chǎn)品變化通告： AD9548 Mask Change 20/Oct/2010
標準包裝： 1
類型： 時鐘/頻率發(fā)生器，同步器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:1
差分 - 輸入:輸出： 是/是
頻率 - 最大： 750kHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 88-VFQFN 裸露焊盤，CSP
供應商設備封裝： 88-LFCSP-VQ（12x12）
包裝： 托盤
Data Sheet
AD9548
Rev. E | Page 39 of 112
samples grows larger. Thus, one way of indicating a locked
condition is to count the number of consecutive in-phase PFD
samples and if it exceeds a certain value, then declare the PLL
locked.
This is exactly the role of the lock detect divider bits. When the lock
detector is enabled (Register 0x0100, Bit 2 = 0), the lock detect
divider bits determine the number of consecutive in-phase
decisions required (128, 256, 512, or 1024) before the lock detector
declares a locked condition. The default setting is 128.
Charge Pump
The charge pump operates in either automatic or manual mode
based on the charge pump mode bit (Register 0x0100, Bit 6).
When Register 0x0100, Bit 6 = 0, the AD9548 automatically
selects the appropriate charge pump current based on the
N-divider value. Note that the user cannot control the charge
pump current bits (Register 0x0100, Bits[5:3]) in automatic
mode. When Register 0x0100, Bit 6 = 1, the user determines the
charge pump current via the charge pump current bits (Register
0x0100, Bits[5:3]). The charge pump current varies from 125 μA
to 1 mA in 125 μA steps. The default setting is 500 μA.
SYSCLK PLL Loop Filter
The AD9548 has an internal second order loop filter that esta-
blishes the loop dynamics for input signals between 12.5 MHz
and 100 MHz. By default, the device uses the internal loop filter.
However, an external loop filter option is available by setting the
external loop filter enable bit (Register 0x0100, Bit 7). This
bypasses the internal loop filter and allows the device to use an
externally connected second order loop filter, as shown in
SYSCLK_VREG
R1
AD9548
SYSCLK_LF
C1
C2
48
49
0
80
22
-02
1
Figure 47. External Loop Filter Schematic
To determine the external loop filter components, the user
decides on the desired open loop bandwidth (fOL) and phase
margin (). These parameters allow calculation of the loop filter
components, as follows:
φ
sin
1
VCO
CP
OL
K
I
Nf
R1
2
2
φ
tan
OL
VCO
CP
f
N
K
I
C1
φ
cos
φ
sin
1
2
OL
VCO
CP
f
N
K
I
C2
where KVCO = 7 × 107 V/ns (typical), ICP is the programmed
charge pump current (amperes), N is the programmed feedback
divider value, fOL is the desired open-loop bandwidth (in hertz),
and Φ is the desired phase margin (in radians).
For example, assuming that N = 40, ICP = 0.5 mA, fOL = 400 kHz,
and Φ = 50°, then the loop filter calculations yield R1 =
3.31 kΩ, C1 = 330 pF, and C2 = 50.4 pF.
System Clock Period
Many of the user programmable parameters of the AD9548 have
absolute time units. To make this possible, the AD9548 requires
a priori knowledge of the period of the system clock. To accom-
modate this requirement, the user programs the 21-bit nominal
system clock period in the nominal SYSCLK period register
(Address 0x0106 to Address 0x0108). The contents of this
register reflect the actual period of the system clock in
femtoseconds. The user must properly program this register to
ensure proper operation of the device because many of its
subsystems rely on this value.
System Clock Stability Timer
The system clock stability timer (Register 0x0106 to Register
0x0108) is a 20-bit value programmed in milliseconds. If the
programmed timer value is 0, then the timer immediately
indicates that it has timed out. If the programmed timer value is
a nonzero value and the SYSCLK PLL is enabled, then the timer
starts timing when the SYSCLK PLL lock detector indicates lock
and times out after the prescribed period. However, when the
user disables the SYSCLK PLL, then the timer ignores the
SYSCLK PLL lock detector and starts timing as soon as the
SYSCLK PLL is disabled. The user can monitor the status of the
stability timer via Register 0x0D01, Bit 4, via the multifunction
pins or via the IRQ pin.
Note that the system clock stability timer must be programmed
before the SYSCLK PLL is either activated or disabled.
SYSCLK PLL Calibration
When using the SYSCLK PLL, it is necessary to calibrate the LC
VCO to ensure that the PLL can remain locked to the system
clock input signal. Assuming the presence of either an external
SYSCLK input signal or a crystal resonator, the calibration
process executes after the user sets and then clears the calibrate
system clock bit in the cal/sync register (Register 0x0A02, Bit 0).
During the calibration process, the device calibrates the VCO
amplitude and frequency. The status of the system clock cali-
bration process is user accessible via the system clock register
(Register 0x0D01, Bit 1). It is also available via the IRQ monitor
register (Register 0D02, Bit 1) provided the status bit is enabled
via the IRQ mask register.
When the calibration sequence is complete, the SYSCLK PLL
eventually attains a lock condition, at which point the system
clock stability timer begins its countdown sequence. Expiration
of the timer indicates that the SYSCLK PLL is stable, which is
reflected in the system clock register (Register 0x0D01, Bit 4).
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