參數(shù)資料
型號(hào)： AD9548BCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 110/112頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK GEN/SYNCHRONIZR 88LFCSP
產(chǎn)品變化通告： AD9548 Mask Change 20/Oct/2010
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： 時(shí)鐘/頻率發(fā)生器，同步器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:1
差分 - 輸入:輸出： 是/是
頻率 - 最大： 750kHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 88-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 88-LFCSP-VQ（12x12）
包裝： 托盤(pán)
Data Sheet
AD9548
Rev. E | Page 97 of 112
Table 128. Incremental Phase Offset Control
Address
Bits
Bit Name
Description
0x0A0C
[7:3]
Unused
[2]
Reset phase offset
Resets the incremental phase offset to 0.
This is an autoclearing bit.
[1]
Decr phase offset
Decrements the incremental phase offset by the amount specified in the
incremental phase lock offset step size register (Register 0x0314 to Register 0x0315).
This is an autoclearing bit.
[0]
Incr phase offset
Increments the incremental phase offset by the amount specified in the
incremental phase lock offset step size register (Register 0x0314 to Register 0x0315).
This is an autoclearing bit.
Table 129. Reference Profile Selection State Machine Startup1
Address
Bits
Bit Name
Description
0x0A0D
[7]
Detect DD
Setting this bit starts the profile selection state machine for Input Reference DD.
[6]
Detect D
Setting this bit starts the profile selection state machine for Input Reference D.
[5]
Detect CC
Setting this bit starts the profile selection state machine for Input Reference CC.
[4]
Detect C
Setting this bit starts the profile selection state machine for Input Reference C.
[3]
Detect BB
Setting this bit starts the profile selection state machine for Input Reference BB.
[2]
Detect B
Setting this bit starts the profile selection state machine for Input Reference B.
[1]
Detect AA
Setting this bit starts the profile selection state machine for Input Reference AA.
[0]
Detect A
Setting this bit starts the profile selection state machine for Input Reference A.
1
All bits in this register are autoclearing.
Table 130. Reference Validation Override Controls1
Address
Bits
Bit Name
Description
0x0A0E
[7]
Force Timeout DD
Setting this bit emulates a timeout of the validation timer for Reference DD.
This is an autoclearing bit.
[6]
Force Timeout D
Setting this bit emulates a timeout of the validation timer for Reference D.
This is an autoclearing bit.
[5]
Force Timeout CC
Setting this bit emulates a timeout of the validation timer for Reference CC.
This is an autoclearing bit.
[4]
Force Timeout C
Setting this bit emulates a timeout of the validation timer for Reference C.
This is an autoclearing bit.
[3]
Force Timeout BB
Setting this bit emulates a timeout of the validation timer for Reference BB.
This is an autoclearing bit.
[2]
Force Timeout B
Setting this bit emulates a timeout of the validation timer for Reference B.
This is an autoclearing bit.
[1]
Force Timeout AA
Setting this bit emulates a timeout of the validation timer for Reference AA.
This is an autoclearing bit.
[0]
Force Timeout A
Setting this bit emulates a timeout of the validation timer for Reference A.
This is an autoclearing bit.
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