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參數(shù)資料
| 型號： | AD9548BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 88LFCSP |
| 產(chǎn)品變化通告： | AD9548 Mask Change 20/Oct/2010 |
| 標準包裝： | 1 |
| 類型： | 時鐘/頻率發(fā)生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 750kHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 88-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 88-LFCSP-VQ（12x12） |
| 包裝： | 托盤 |
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Data Sheet
AD9548
Rev. E | Page 103 of 112
Table 145. EEPROM Storage Sequence for General Configuration Settings
Address
Bits
Bit Name
Description
0x0E15
[7:0]
General
The default value of this register is 0x14, which the controller interprets as a data
instruction. Its decimal value is 20, which tells the controller to transfer 21 bytes of
data (20 + 1) beginning at the address specified by the next two bytes. The
controller stores 0x14 in the EEPROM and increments the EEPROM address pointer.
0x0E16
[7:0]
General
The default value of these two registers is 0x0200. Note that Register 0x0E16 and
Register 0x0E17 are the most significant and least significant bytes of the target
address, respectively. Because the previous register contains a data instruction,
these two registers define a starting address (in this case, 0x0200). The controller
stores 0x0200 in the EEPROM and increments the EEPROM pointer by 2. It then
transfers 21 bytes from the register map (beginning at Address 0x0200) to the
EEPROM and increments the EEPROM address pointer by 22 (21 data bytes and
one checksum byte). The 21 bytes transferred correspond to the general
configuration parameters in the register map.
0x0E17
[7:0]
Table 146. EEPROM Storage Sequence for DPLL Settings
Address
Bits
Bit Name
Description
0x0E18
[7:0]
DPLL
The default value of this register is 0x1B, which the controller interprets as a data
instruction. Its decimal value is 27, which tells the controller to transfer 28 bytes
of data (27 + 1) beginning at the address specified by the next two bytes. The
controller stores 0x1B in the EEPROM and increments the EEPROM address pointer.
0x0E19
[7:0]
DPLL
The default value of these two registers is 0x0300. Note that Register 0x0E19 and
Register 0x0E1A are the most significant and least significant bytes of the target
address, respectively. Because the previous register contains a data instruction,
these two registers define a starting address (in this case, 0x0300). The controller
stores 0x0300 in the EEPROM and increments the EEPROM pointer by 2. It then
transfers 28 bytes from the register map (beginning at Address 0x0300) to the
EEPROM and increments the EEPROM address pointer by 29 (28 data bytes and
one checksum byte). The 28 bytes transferred correspond to the DPLL parameters
in the register map.
0x0E1A
[7:0]
Table 147. EEPROM Storage Sequence for Clock Distribution Settings
Address
Bits
Bit Name
Description
0x0E1B
[7:0]
Clock distribution
The default value of this register is 0x19, which the controller interprets as a data
instruction. Its decimal value is 25, which tells the controller to transfer 26 bytes of
data (25 + 1) beginning at the address specified by the next two bytes. The
controller stores 0x19 in the EEPROM and increments the EEPROM address pointer.
0x0E1C
[7:0]
Clock distribution
The default value of these two registers is 0x0400. Note that Register 0x0E1C and
Register 0x0x0E1D are the most significant and least significant bytes of the target
address, respectively. Because the previous register contains a data instruction,
these two registers define a starting address (in this case, 0x0400). The controller
stores 0x0400 in the EEPROM and increments the EEPROM pointer by 2. It then
transfers 26 bytes from the register map (beginning at Address 0x0400) to the
EEPROM and increments the EEPROM address pointer by 27 (26 data bytes and
one checksum byte). The 26 bytes transferred correspond to the clock distribution
parameters in the register map.
0x0E1D
[7:0]
0x0E1E
[7:0]
I/O update
The default value of this register is 0x80, which the controller interprets as an I/O
update instruction. The controller stores 0x80 in the EEPROM and increments the
EEPROM address pointer.
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| AD9548BCPZ-REEL7 | 功能描述:IC CLOCK GEN/SYNCHRONIZR 88LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應商設備封裝:64-TSSOP 包裝:管件 |
| AD9548XCPZ | 制造商:Analog Devices 功能描述: |
| AD9549 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Input Network Clock Generator/Synchronizer |
| AD9549/PCBZ | 制造商:Analog Devices 功能描述:DUAL INPUT NETWORK CLOCK GEN/SYNCHRONIZER - Bulk |
| AD9549A/PCBZ | 功能描述:BOARD EVALUATION FOR AD9549A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
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