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參數(shù)資料
| 型號： | AD9548BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 50/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 88LFCSP |
| 產(chǎn)品變化通告： | AD9548 Mask Change 20/Oct/2010 |
| 標準包裝： | 1 |
| 類型： | 時鐘/頻率發(fā)生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 750kHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 88-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 88-LFCSP-VQ（12x12） |
| 包裝： | 托盤 |
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AD9548
Data Sheet
Rev. E | Page 42 of 112
then clears the bit. The synchronization event is the clearing
operation; that is, the Logic 1 to Logic 0 transition of the bit.
The primary synchronization signal can synchronize the distri-
bution output directly or it can enable a secondary synchronization
signal. This functionality depends on the two sync source bits in
the distribution synchronization register (Register 0x0402,
Bits[5:4]).
When sync source = 00 (direct), the falling edge of the primary
synchronization signal synchronizes the distribution output
directly.
When sync source = 01, the rising edge of the primary synch-
ronization signal triggers the circuitry that detects a rising edge
of the active input reference. The detection of the rising edge is
what synchronizes the distribution output.
When sync source = 10, the rising edge of the primary synch-
ronization signal triggers the circuitry that detects a rollover of
the DDS accumulator (after processing by the DPLL feedback
divider). This corresponds to the zero crossing of the output of
the phase-to-amplitude converter in the DDS (less the open-
loop phase offset stored in Register 0x030D to Register 0x030E).
The detection of the DPLL feedback edge is what synchronizes
the distribution output.
Active Reference Synchronization (Zero Delay)
Active reference synchronization is the term applied to the case
when sync source = 01 (Register 0x0402, Bits[5:4]). Referring to
Figure 49, this means that the active reference sync path is
active because Bit 4 = 1, enabling the lower AND gate and
disabling the upper AND gate. The edge detector in the active
reference sync block monitors the rising edges of the active
reference (the mux selects the active reference automatically).
The edge detector is armed via the primary synchronization
signal, which is one of the four inputs to the OR gate (typically
the direct sync source). As soon as the edge detector is armed,
its output goes high, which stalls the output dividers in the
clock distribution block. Furthermore, once armed, a rising
edge from the active reference forces the output of the edge
detector low. This restarts the output dividers, thereby
synchronizing the clock distribution block.
The term zero delay applies because it provides a means to edge
align the output signal with the active input reference signal.
Typically, zero-delay architectures use the output signal in the
feedback loop of a PLL to track input/output edge alignment.
Active reference synchronization, however, operates open loop.
That is, synchronization of the output via the distribution
synchronization logic occurs on a single edge of the active
reference.
The fact that an active reference edge triggers the falling edge of
the synchronization pulse means that the falling edge is
asynchronous to the signal that clocks the distribution output
dividers (CLKINx). Therefore, the output clock distribution
logic reclocks the internal synchronization pulse to synchronize
it with the CLKINx signal. This means that the output dividers
restart after a deterministic delay associated with the reclocking
circuitry. This deterministic delay has two components. The
first deterministic delay component is four or five periods of the
CLKINx signal. The one period uncertainty is due to the
unknown position of the asynchronous reference clock edge
relative to the CLKINx signal. The second deterministic delay
component is one output period of the distribution divider.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9548BCPZ-REEL7 | 功能描述:IC CLOCK GEN/SYNCHRONIZR 88LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD9548XCPZ | 制造商:Analog Devices 功能描述: |
| AD9549 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Input Network Clock Generator/Synchronizer |
| AD9549/PCBZ | 制造商:Analog Devices 功能描述:DUAL INPUT NETWORK CLOCK GEN/SYNCHRONIZER - Bulk |
| AD9549A/PCBZ | 功能描述:BOARD EVALUATION FOR AD9549A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
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