參數(shù)資料
型號(hào)： AD9548BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 31/112頁
文件大?。?/td> 0K
描述： IC CLOCK GEN/SYNCHRONIZR 88LFCSP
產(chǎn)品變化通告： AD9548 Mask Change 20/Oct/2010
標(biāo)準(zhǔn)包裝： 1
類型： 時(shí)鐘/頻率發(fā)生器，同步器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:1
差分 - 輸入:輸出： 是/是
頻率 - 最大： 750kHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 88-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 88-LFCSP-VQ（12x12）
包裝： 托盤
Data Sheet
AD9548
Rev. E | Page 25 of 112
Program the Clock Distribution Outputs
The clock distribution parameters reside in the 0x0400 register
address space. They include the following:
Output power-down control
Output enable (disabled by default)
Output synchronization
Output mode control
Output divider functionality
Program the Reference Inputs
The reference input parameters reside in the 0x0500 register
address space. They include the following:
Reference power-down
Reference logic family
Reference profile assignment control
Phase build-out control
Program the Reference Profiles
The reference profile parameters reside in the 0x0600 to 0x0700
register address space. They include the following:
Reference priority
Reference period
Reference period tolerance
Reference validation timer
Reference redetect timer
Digital loop-filter coefficients
Reference prescaler (R-divider)
Feedback dividers (S, U, and V)
Phase and frequency lock detector controls
Generate the Reference Acquisition
After the registers are programmed, issue an I/O update using
Register 0x0005, Bit 0 to invoke all of the register settings
programmed up to this point.
If the settings are programmed for manual profile assignment,
the DPLL locks to the first available reference that has the
highest priority. If the settings are programmed for automatic
profile assignment, then write to the reference profile detect
register (Address 0x0A0D) to select the state machines that
require starting. Next, issue an I/O update (Address 0x0005, Bit
0) to start the selected state machines. Upon completion of the
reference detection sequence, the DPLL locks to the first
available reference with the highest priority.
Generate the Output Clock
If the registers are programmed for automatic clock distribution
synchronization via DPLL phase or frequency lock, the syn-
thesized output signal appears at the clock distribution outputs
(assuming the output is enabled and that the DDS output signal
has been routed to the CLKIN input pins). Otherwise, set and
then clear the sync distribution bit (Address 0x0A02, Bit 1) or
use a multifunction pin input (if programmed accordingly) to
generate a clock distribution sync pulse, which causes the
synthesized output signal to appear at the clock distribution
outputs.
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