參數(shù)資料
型號(hào)： AD9548BCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 48/112頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK GEN/SYNCHRONIZR 88LFCSP
產(chǎn)品變化通告： AD9548 Mask Change 20/Oct/2010
標(biāo)準(zhǔn)包裝： 1
類型： 時(shí)鐘/頻率發(fā)生器，同步器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:1
差分 - 輸入:輸出： 是/是
頻率 - 最大： 750kHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 88-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 88-LFCSP-VQ（12x12）
包裝： 托盤
AD9548
Data Sheet
Rev. E | Page 40 of 112
Note that the monitors/detectors associated with the input
references (REFA/AA – REFD/DD) are internally disabled until
the SYSCLK PLL indicates that it is stable.
CLOCK DISTRIBUTION
The clock distribution block of the AD9548 provides an
integrated solution for generating multiple clock outputs based
on frequency dividing the DPLL output. The distribution
output consists of four channels (OUT0 to OUT3). Each of the
four output channels has a dedicated divider and output driver,
as appears in Figure 48.
Q0
SYNC
CONTROL
ENABLEn/MODEn
SYNC SOURCE
CLKINP
OUT1P
OUT1N
OUT2P
OUT2N
OUT3P
OUT3N
OUT1
OUT3
OUT2
OUT0
CLKINN
OUT_RSET
OUT0P
OUT0N
R
ESE
T
E
NABL
E
4
08
02
2-
02
2
Figure 48. Clock Distribution
Clock Input (CLKINx)
The clock input handles input signals from a variety of logic
families (assuming proper terminations and sufficient voltage
swing). It also handles sine wave input signals such as those
delivered by the DAC reconstruction filter. Its default operating
frequency range is 62.5 MHz to 500 MHz.
Super-Nyquist Operation
Typically, the maximum usable frequency at the DAC output is
about 45% of the system clock frequency. However, because it is
a sampled DAC, its output spectrum contains Nyquist images.
Of particular interest are the images appearing in the first Nyquist
zone (50% to 100% of the system clock frequency). Super-
Nyquist operation takes advantage of these higher frequencies,
but this implies that the CLKINx input operates in excess of
500 MHz, which is outside of its default operating limits.
The CLKINx receiver actually consists of two separate receivers:
the default receiver and an optional high frequency receiver,
which handles input signals up to 800 MHz. To select the high
frequency receiver, write a Logic 1 to Register 0x0400, Bit 4.
Super-Nyquist operation requires a band-pass filter at the DAC
output instead of the usual low-pass reconstruction filter. Super-
Nyquist operation is viable as long as the image frequency does
not exceed the 800 MHz input range of the receiver. Furthermore,
to provide acceptable jitter performance, which is a consideration
for image signals with low amplitude, the signal at the CLKINx
input must meet the minimum slew rate requirements.
Clock Dividers
The output clock distribution dividers are referred to as Q0 to Q3,
corresponding to the OUT0 to OUT3 output channels, respectively.
Each divider is programmable with 30 bits of division depth. The
actual divider ratio is one more than the programmed register
value; therefore, a register value of 3, for example, results in a
divide ratio of 4. Thus, each divider offers a range of divide
ratios from 1 to 230 (1 to 1,073,741,824).
With an even divide ratio, the output signal always exhibits a
50% duty cycle. When the clock divider is bypassed (a divide
ratio of 1), the output duty cycle is the same as the input duty
cycle. Odd output divide ratios (excluding 1) exhibit automatic
duty cycle correction given by
N
X
N
Cycle
Duty
Output
2
1
2
where N (which must be an odd number) is the divide ratio and
X is the normalized fraction of the high portion of the input
period (that is, 0 < X < 1).
For example, if N = 5 and the input duty cycle is 20% (X = 0.2),
then the output duty cycle is 44%. Note that, when the user programs
an output as noninverting, then the device adjusts the falling
edge timing to accomplish the duty cycle correction. Conversely,
the device adjusts the rising edge timing for an inverted output.
Output Power-Down
Each of the output channels offers independent control of
power-down functionality via the distribution settings register
(Address 0x0400). Each output channel has a dedicated power-
down bit for powering down the output driver. However, if all
four outputs are powered down, the entire distribution output
enters a deep sleep mode.
Even though each channel has a channel power-down control
signal, it may sometimes be desirable to power down an output
driver while maintaining the divider’s synchronization with the
other channel dividers. This is accomplished by either of the
following methods:
In CMOS mode, use the divider output enable control bit
to stall an output. This provides power savings while
maintaining dc drive at the output.
In LVDS/LVPECL mode, place the output in tristate mode
(this works in CMOS mode as well).
Output Enable
Each of the output channels offers independent control of enable/
disable functionality via the distribution enable register
(Address 0x0401). The distribution outputs use synchronization
logic to control enable/disable activity to avoid the production
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