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參數(shù)資料
| 型號： | AD9548BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 30/112頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 88LFCSP |
| 產(chǎn)品變化通告： | AD9548 Mask Change 20/Oct/2010 |
| 標準包裝： | 1 |
| 類型： | 時鐘/頻率發(fā)生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 750kHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 88-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 88-LFCSP-VQ（12x12） |
| 包裝： | 托盤 |
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AD9548
Data Sheet
Rev. E | Page 24 of 112
GETTING STARTED
POWER-ON RESET
The AD9548 monitors the voltage on the power supplies at
power-up. When DVDD3 is greater than 2.35 V ± 0.1 V and
DVDD (Pin 1, Pin 6, Pin 12, Pin 77, Pin 83, and Pin 88) is
greater than 1.4 V ± 0.05 V, the device generates a 75 ns reset
pulse. The power-up reset pulse is internal and independent of
the RESET pin. This internal power-up reset sequence eliminates
the need for the user to provide external power supply sequencing.
Within 45 ns after the leading edge of the internal reset pulse,
the M0 to M7 multifunction pins behave as high impedance
digital inputs and remain so until programmed otherwise.
INITIAL PIN PROGRAMMING
During a device reset (either via the power-up reset pulse or the
RESET pin), the multifunction pins (M0 to M7) behave as high
impedance inputs, but upon removal of the reset condition,
level-sensitive latches capture the logic pattern present on the
multifunction pins. The AD9548 requires that the user supply
the desired logic state to the M0 to M7 pins by means of pull-up
and/or pull-down resistors (nominally 10 kΩ to 30 kΩ).
The initial state of the M0 to M7 pins following a reset is
referred to as FncInit, Bits[7:0]. Bits[7:0] of FncInit map directly
to the logic states of M7:0, respectively. The three LSBs of
FncInit (FncInit, Bits[2:0]) determine whether the serial port
interface behaves according to the SPI or I2C protocol.
Specifically, FncInit, Bits[2:0] = 000 selects the SPI interface,
while any other value selects the I2C port with the three LSBs of
the I2C bus address set to the value of FncInit, Bits[2:0].
The five MSBs of FncInit (FncInit, Bits[7:3]) determine the
operation of the EEPROM loader. On the falling edge of RESET,
if FncInit, Bits[7:3] = 00000, then the EEPROM contents are not
transferred to the control registers and the device registers
assume their default values. However, if FncInit, Bits[7:3] ≠
00000, then the EEPROM controller transfers the contents of
the EEPROM to the control registers with condition = FncInit,
Bits[7:3] (see the EEPROM section).
DEVICE REGISTER PROGRAMMING
The initial state of the M0 to M7 pins establishes the serial I/O
port protocol (SPI or I2C). Using the appropriate serial port
protocol, and assuming that an EEPROM download is not used,
program the device according to the recommended sequence
described in the Program the System Clock Functionality
section through the Generate the Output Clock section.
Program the System Clock Functionality
The system clock parameters reside in the 0100 register address
space. They include the following:
System clock PLL controls
System clock period
System clock stability timer
It is essential to program the system clock period because many of
the AD9548 subsystems rely on this value. It is highly recommended
to program the system clock stability timer, as well. This is
especially important when using the system clock PLL but also
applies if using an external system clock source, especially if the
external source is not expected to be completely stable when
power is applied to the AD9548.
Initialize the System Clock
After the system clock functionality is programmed, issue an
I/O update using Register 0x0005, Bit 0 to invoke the system
clock settings.
Calibrate the System Clock (Only if Using SYSCLK PLL)
Set the calibrate system clock bit in the sync/cal register
(Address 0x0A02, Bit 0) and issue an I/O update. Then clear the
calibrate system clock bit and issue another I/O update. This
action allows time for the calibration to proceed while pro-
gramming the remaining device registers.
Program the Multifunction Pins (Optional)
This step is required only if the user intends to use any of the
multifunction pins for status or control. The multifunction pin
parameters reside in the 0x0200 to 0x0207 register address
space. The default configuration of the multifunction pins is as
an undesignated high impedance input pin.
Program the IRQ Functionality (Optional)
This step is required only if the user intends to use the IRQ feature.
IRQ control resides in the 0x0200 to 0x0207 register address space.
It includes the following:
IRQ pin mode control
IRQ mask
The IRQ mask default values prevent interrupts from being
generated. The IRQ pin mode default is open-drain NMOS.
Program the Watchdog Timer (Optional)
This step is required only if the user intends to use it. Watchdog
timer control resides in the 0x0200 register address space. The
watchdog timer is disabled by default.
Program the DAC Full-Scale Current (Optional)
This step is required only if the user intends to use a full-scale
current setting other than the default value. DAC full-scale
current control resides in the 0x0200 register address space.
Program the Digital Phase-Locked Loop (DPLL)
The DPLL parameters reside in the 0x0300 register address
space. They include the following:
Free-run frequency (DDS frequency tuning word)
DDS phase offset
DPLL pull-in range limits
DPLL closed-loop phase offset
Phase slew control (for hitless reference switching)
Tuning word history control (for holdover operation)
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| AD9548BCPZ-REEL7 | 功能描述:IC CLOCK GEN/SYNCHRONIZR 88LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD9548XCPZ | 制造商:Analog Devices 功能描述: |
| AD9549 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Input Network Clock Generator/Synchronizer |
| AD9549/PCBZ | 制造商:Analog Devices 功能描述:DUAL INPUT NETWORK CLOCK GEN/SYNCHRONIZER - Bulk |
| AD9549A/PCBZ | 功能描述:BOARD EVALUATION FOR AD9549A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
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