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參數(shù)資料
| 型號： | 84302 |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器) |
| 中文描述： | 4端口快速以太網(wǎng)控制器（4端口快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 8/96頁 |
| 文件大?。?/td> | 826K |
| 代理商： | 84302 |
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84302 4-Port
Fast Ethernet Controller
4-8
MD400171/C
Pin #
18
Pin Name
BUSSIZE
I/O
I
Description
Register Interface Bus Size Select.
1 = Register Interface Bus is 16-Bits Wide (CDST[15:0])
0 = Register Interface Bus is 8-Bits Wide (CDST[7:0])
14
13
BE1
BE0
I
Register Byte Enable Inputs.
These inputs determine which bytes of
the current 16-bit word on CDST[15:0] contain valid data. These inputs
are clocked in on falling edges of WR and RD.
11 = No Valid Data
10 = Valid data on CDST[7:0]
01 = Valid data on CDST[15:8]
00 = Valid data on CDST[15:0]
Register Data Input.
These bidirectional bus is the 16-bit data path to
and from the internal registers for a selected port. Data is read/written
from/to the internal registers on falling edges of WR and RD.
These pins are high impedance until their output drivers are enabled by
RD and ENREGIO being asserted low.
Note:
Pin #35 = CDST 15, Pin #54 = CDST 0
Register Ready Indication Output.
This active high output indicates
that data being read out on CDST[15:0] is valid. READY goes active
high after RD has been asserted, and will stay high until RD is
deasserted. READY goes into High Impedance State when ENREGIO
is deasserted.
Interrupt Output.
These outputs, one per port, are asserted active high
when certain interrupt bits are asserted. These pins remain latched high
until all interrupt bits causing the interrupt condition are read.
35 36 37
38 39 42
43 44 45
46 47 50
51 52 53
54
57
CDST[15:0]
I/O
READY
O
34
33
32
31
INT_1
INT_2
INT_3
INT_4
O
Miscellaneous
174
197
220
243
FDUPLX_1
FDUPLX_2
FDUPLX_3
FDUPLX_4
I
Full Duplex Mode Input.
1 = Half Duplex
0 = Full Duplex
Full Duplex mode can also be selected by setting the Full Duplex bit in
the Configuration 2 register. Half Duplex mode is selected when both
this pin and the Full Duplex mode bit are set to Half Duplex.
One Try Transmit Mode Input.
58
ONETRYMODE
I
Pull
down
1 = No transmission retry attempted after a collision
0 = Normal
Hardware Reset Input.
10
RESET
I
1 = Normal
0 = Device Reset, FIFO’s Cleared, Counters Cleared, Register Bits
Set to Defaults.
1.0 Pin Description (continued)
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