參數(shù)資料
型號(hào)： 84302
廠商： LSI Corporation
英文描述： 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器)
中文描述： 4端口快速以太網(wǎng)控制器（4端口快速以太網(wǎng)控制器）
文件頁(yè)數(shù)： 32/96頁(yè)
文件大?。?/td> 826K
代理商： 84302
84302 4-Port
Fast Ethernet Controller
4-32
MD400171/C
A complete list of the counters along with their definitions
is shown in Table 11. The exact correspondence of the
actual MIB objects from the above IETF and IEEE speci-
fications to the actual 84302 counters locations is de-
scribed in the Applications section and is shown there in
Tables 38-41.
The current count for each counter is stored in individual
Counter Registers. The address ocation or each Counter
Register is also shown in Table 11. Note that all the
counters are 32-bit ong but the Counter Register ength s
only 16-bit. The entire 32-bits can be read out of he device
by doing two successive 16-bit reads from the same
address (or 4 reads if BUSSIZE is set for 8-bit bus width).
The first 16-bit read outputs the upper 16-bits (MS byte),
the second 16-bit word outputs the ower 16-bits (LS byte).
Each counter is responsible for tabulating the number of
times a specific event occurs. When a counter s read out,
the count can be automatically reset to 0 or it can remain
unchanged (programmable). Counters can be configured
to either stop counting when they reach their maximum
count or rollover (programmable). When a counter read
operation is initiated, the 32-bit counter result to be ac-
cessed is transferred to two internal 16-bit holding regis-
ters. These holding registers freeze and store the counter
result for the duration of the read operation while allowing
the internal counter to continue to increment if needed.
Counter Overflow
Each 32-bit counter has a status output bit associated with
that counter. The status output bits are stored in the
Counter Status 0-6 registers. These status bits are set
when the counter value reaches 80000000H (i.e. MSB bit
goes from a 0 to a 1). Thus, the status bits are set when
the counter becomes half full.
The counter status bits stay atched high until hey read out
(R/LHI bits). When a counter status bit s read out, t s hen
cleared ow. Counter status bits are also nterrupt bits; hat
is, the setting of any counter status bit will cause the
assertion of the nterrupt pin, INT_[1:4] for that port. When
a counter status bit s read, the nterrupt caused by that bit
is cleared. Note that INT_[1:4] stays asserted until all
interrupt bits are cleared. Each counter status bit can be
individually programmed to not assert interrupt by setting
the mask bit associated with that counter bit in Counter
Interrupt Enable 1-7 registers.
Counter Reset On Read
The counter value is normally unaffected by a read
operation on that counter. However, the counters can be
programmed to automatically reset the count to 0 when
read out by setting the counter reset on read bit in the
Configuration 3 Register. When this bit is set high, the
counter s reset to 0 when read out; when this bit s cleared
low, the count inside the counters is unaffected by a read
as long as the counter is not at maximum count. If a
counter is at maximum count, it’s count is always reset to
0’s when it is read out.
Counter Rollover
The counters normally rollover to 0 when they exceed their
maximum count (i.e. receive an ncrement when counter s
at maximum count). The counters can be programmed to
freeze and stop counting once they reach their maximum
count by setting he counter rollover bit n he Configuration
3 register.
Maximum Packet Size
The maximum packet size used for the management
counter statistics can be set to any value between 1518-
1533 bytes by appropriately setting the counter maximum
packet size select bit n he Configuration 4 register and he
maximum packet size select bits in Configuration 5 regis-
ter. The maximum packet size default is 1518 bytes.
Counter Reset
All counters, for a given port, can be reset to all 0’s by
setting and then clearing the counter reset bit in the
Configuration 4 register for that port. Asserting the device
reset pin RESET will also set the counter reset bits to their
default values of 1 and subsequently force the counters in
all ports to 0. When this device reset occurs, the counter
reset bits will be set to their default value of 1, and they
must be cleared to 0, on each port, n order for the counters
on that port to be functional.
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