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參數(shù)資料
| 型號： | 84302 |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器) |
| 中文描述： | 4端口快速以太網(wǎng)控制器（4端口快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 28/96頁 |
| 文件大?。?/td> | 826K |
| 代理商： | 84302 |
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84302 4-Port
Fast Ethernet Controller
4-28
MD400171/C
MDC Cycle Time
The MDC clock period is programmable and is a function
of (1) the system clock period, SLCK, and (2) the clock
period select bits in the MI Command/Status 0 register
according to the equation shown in the MI Command/
Status 0 register definition table.
FULL DUPLEX
General
Half Duplex mode is the normal CSMA/CD operation
defined in IEEE 802.3. Full Duplex operation is a mode
that allows transmission and reception to occur simulta-
neously. As such, when the device s placed n Full Duplex
mode, the collision function is disabled and the loopback
of transmit to receive (TXEN to CRS) caused by the
external Physical Layer device has to be ignored.
Enabling Full Duplex
The device can be placed in Full Duplex mode, on a per
port basis, by either setting the FDUPLX_[1:4] pin for that
port to Full Duplex mode or by setting the Full Duplex
select bit in the Configuration 1 register for that port to Full
Duplex mode. The interaction of the pin and bit is de-
scribed in Table 9. Note that both the pin and bit must be
set to Half Duplex for Half Duplex mode to be selected.
Table 9. FDX Bit & FDUPLX Pin Logic
FDX Bit in
Config. 1 Reg.
1=Full Duplex
0=Half Duplex
FDUPLX
Pin
1=Half Duplex
0=Full Duplex
1
1
Full Duplex
1
0
Full Duplex
0
1
Half Duplex
0
0
Full Duplex
Full Duplex Indication
The Duplex state of the device, either Full or Half, is
reported on the duplex status bit in the Miscellaneous
Status register.
Loopback Disable
In Half Duplex operation, an external PHY device will
always oopback a transmit packet to the receive side over
the PHY nterface. This oopbacked receive packet can be
automatically ignored and discarded by setting the Re-
ceive Own Transmit Ignore bit in the Configuration 1
register.
Symbol
IDLE[31:0]
Name
Idle Pattern
I/O
O
Definition
These 32 bits are always 1’s, and they provide
the necessary spacing between MI data transfer
cycles.
These two bits always contain the 01 pattern.
This bit pattern (following an Idle Pattern) signals
the start of an MI data transfer cycle.
10 = Read Cycle
01 = Write Cycle
These bits contain the address of the external
PHY that is selected for the MI data transfer.
These bits contain the address of the register in
the external PHY that is selected for the MI data
transfer.
These bits provide some turnaround time for
MDIO between write and read operations.
For Write Cycle Output TA[1:0] = 10
For Read Cycle, Input TA[1:0] = Z0
These 16 bits contain data to/from the selected
register in the selected external PHY.
Where Bits Come From
Internally Generated
ST1
ST0
Start Bits
O
Internally Generated
OP1
OP0
PHYAD[4:0]
Opcode Select
O
MI Command/Status 1
Register
MI Command/Status 1
Register
MI Command/Status 0
Register
Physical Device
Address
O
REGAD4[4:0] Register Address
O
TA1
TA0
Turnaround
Time
I/O
Internally Generated
D[15:0]
Data
I/O
MI Data 0-1 Registers
IDLE31 is shifted out first on MDIO
Table 8. MI Bit Definitions
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