參數(shù)資料
型號(hào)： 84302
廠商： LSI Corporation
英文描述： 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器)
中文描述： 4端口快速以太網(wǎng)控制器（4端口快速以太網(wǎng)控制器）
文件頁(yè)數(shù)： 5/96頁(yè)
文件大?。?/td> 826K
代理商： 84302
84302 4-Port
Fast Ethernet Controller
4-5
MD400171/C
Pin #
75 76 77
78 81 82
83 84 87
88 89 90
93 94 95
96 102
103 104
105 108
109 110
111 114
115 116
117 120
121 122
123
131
139
147
155
Pin Name
RXTXDATA[31:0]
I/O
I/O
Description
Receive-Transmit Data Input/Output.
This bidirectional bus contains
data read or written to/from the FIFO’s for the selected port. During
receive reads, these pins are outputs and contain data read from the
receive FIFO. During transmit reads, these pins are inputs and contain
data to be written to the transmit FIFO. RXTXDATA[31:0] is clocked
in/out on rising edges of the system clock, SCLK.
Note:
Pin #75 = RXTXDATA 31, Pin #123 = RXTXDATA 0
RXABORT_1
RXABORT_2
RXABORT_3
RXABORT_4
I
Receive Abort Input.
1 = Abort Packet, Discard RX FIFO Data, Block RX FIFO Input
Until Start of Next Packet.
0 = No Discard
These inputs, one per port, are clocked in on rising edges of the system
clock, SCLK.
Receive Discard Output.
135
143
151
159
RXDC_1
RXDC_2
RXDC_3
RXDC_4
O
1 = RX FIFO Data Discarded Due to Receive Error
0 = No Discard
RXDC_[1:4], one per port, are clocked out on rising edges of the system
clock, SCLK, and are placed in high impedance state when RXINTEN
is deasserted. RXDC_[1:4] are latched high until cleared with the
CLRRXERR pin. As long as RXDC_[1:4] is latched high, no new
packets will be loaded into the receive FIFO.
Transmit Retry Output.
136
144
152
160
TXRET_1
TXRET_2
TXRET_3
TXRET_4
O
1 = TX FIFO Data Discarded Due to Transmit Error
0 = No Discard
TXRET_[1:4], one per port, are clocked out on rising edges of the system
clock, SCLK, and are placed in high impedance state when TXINTEN
is deasserted. TXRET_[1:4] are latched high until it is cleared with the
CLRTXERR pin. As long as TXRET_[1:4] are latched high, no new
packets can be transmitted out of the transmit FIFO.
Clear Receive Error Input.
68
CLRRXERR
I
1 = RXDC_[1:4] Pin for Selected Port is Cleared Low
0 = Not Cleared
This input is clocked in on rising edges of the system clock, SCLK .
1.0 Pin Description (continued)
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