參數(shù)資料
型號(hào)： 84302
廠商： LSI Corporation
英文描述： 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器)
中文描述： 4端口快速以太網(wǎng)控制器（4端口快速以太網(wǎng)控制器）
文件頁(yè)數(shù)： 3/96頁(yè)
文件大小： 826K
代理商： 84302
84302 4-Port
Fast Ethernet Controller
4-3
MD400171/C
Pin #
System Interface
61
Pin Name
I/O
Description
RXINTEN
I
Receive Interface Enable Input.
This active low input enables the
System Interface for a receive operation and activates the output drivers
on RXDC_[1:4] and RXRDY_[1:4]. This input is clocked in on
rising edges of the system clock, SCLK.
Transmit Interface Enable Input.
This active low input enables the
System Interface for a receive operation and activates the output drivers
on TXRET_[1:4] and TXRDY_[1:4]. This input is clocked in on
rising edges of the system clock, SCLK.
Receive Read Enable Input.
This input has to be asserted active low
(along with RXINTEN) in order for data on RXTXDATA[31:0] to be
read from the receive FIFO for the selected port. This input is clocked
in on rising edges of the system clock, SCLK.
Transmit Write Enable Input.
This input has to be asserted active low
(along with TXINTEN) in order for data on RXTXDATA[31:0] to be
written into the transmit FIFO for the selected port. This input is clocked
in on rising edges of the system clock, SCLK.
System Interface Clock Input.
This input clocks data in and out of the
receive and transmit FIFO’s on RXTXDATA[31:0]. All System
Interface inputs and outputs are also clocked in and out on rising edges
of SCLK. The SCLK clock frequency must be between 25-50 Mhz.
Port Select Input.
These inputs select which of the four ports will be
accessed on the System Interface.
11 = Port 4 Accessed Over System Interface
10 = Port 3 Accessed Over System Interface
01 = Port 2 Accessed Over System Interface
00 = Port 1 Accessed Over System Interface
Receive-Transmit Byte Enable Input/Output.
These bidirectional
signals indicate which bytes of the current 32-bit data word on
RXTXDATA[31:0] contain valid data.
When the device is selected for a transmit FIFO write operation to a
selected port, these pins are configured as inputs and indicate which
bytes on RXTXDATA contain valid data.
When the device is selected for a receive FIFO read operation from a
selected port, these pins can be configured to be either inputs or outputs,
depending on how they are programmed via an internal register bit. If
they are configured as inputs, they dictate which bytes the data
from the receive FIFO will be read out on. When configured as outputs,
these pins indicated which bytes contain valid data.
RXTXBE[3:0] is clocked in/out on rising edges of the system clock SCLK.
Receive FIFO Ready Output.
These outputs, one per port, indicate
that the RX FIFO data has either exceeded the programmable threshold
value or an end of a packet was loaded into the RX FIFO. These outputs
are clocked out on rising edges of the system clock, SCLK, and are
put in high impedance state when RXINTEN is deasserted.
1 = RX FIFO Data
≥
RXFIFO Threshold
Or
End Of Frame Loaded Into RX FIFO
0 = Below Threshold
62
TXINTEN
I
65
RXRDEN
I
66
TXWREN
I
99
SCLK
I
60
59
RXTXPS1
RXTXPS0
I
69
70
71
72
I/O
133
141
149
157
RXRDY_1
RXRDY_2
RXRDY_3
RXRDY_4
O
1.0 Pin Description
RXTXBE3
RXTXBE2
RXTXBE1
RXTXBE0
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