參數(shù)資料
型號(hào)： 84302
廠商： LSI Corporation
英文描述： 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器)
中文描述： 4端口快速以太網(wǎng)控制器（4端口快速以太網(wǎng)控制器）
文件頁(yè)數(shù)： 23/96頁(yè)
文件大?。?/td> 826K
代理商： 84302
84302 4-Port
Fast Ethernet Controller
4-23
MD400171/C
RECEIVE FIFO
General
The receive FIFO acts as a temporary buffer between the
receive MAC section and System Interface. The receive
FIFO size is 128 bytes. Data is clocked into the receive
FIFO with the PHY Interface TXC clock. Data is clocked
out of the receive FIFO with theSystem Interface clock,
SCLK. There s one programmable watermark output and
one almost full output which aid in managing the data flow
out of the receive FIFO.
Watermarks
There is one watermark for the receive FIFO. This water-
mark is output on the RXRDY pin. This watermark is
asserted when the receive FIFO data exceeds or equals
the thresholds associated with the watermark.
The receive watermark threshold for RXRDY and can be
programmed over the entire 128 byte receive FIFO range.
The watermark threshold can be programmed with four
bits that reside in the FIFO Threshold register. Once the
data in the FIFO exceeds or equals the threshold of the
watermark, then the watermark pin on RXRDY s asserted
active high. RXRDY is also asserted if a complete packet
is loaded into the receive FIFO from the MII. The water-
mark stays asserted until the data in the FIFO goes below
the programmable threshold.
Almost Empty Indication
There is an almost empty output indication for the the
receive FIFO on the SPDTAVL pin. When a RX FIFO read
operation is in progress, the SPDTAVL ouput pin will be
asserted active low if there is less than 3 double words of
data in the receive FIFO.
RX Overflow
The receive FIFO overflow condition occurs when the
receive RX FIFO is full and additional data is still being
written nto t from the MAC. If the receive FIFO overflows,
then (1) RXDC is asserted and latched, (2) all data in the
RX FIFO is discarded, (3) all input data to the RX FIFO is
blocked until he RXDC signal s cleared with CLRRXERR,
(4) the RX FIFO overflow bit is set as an indication of this
condition n the RX Status register, and (5) the nterrupt pin
is asserted for that port provided the interrupt function is
enabled. Refer to the Packet Discard section for more
information about discards. The device can be pro-
grammed to not discard and subsequently accept all
packets corrupted by overflow by setting the RX FIFO
overflow bit in the RX Command register.
Discards
Certain error conditions detected for a given packet will
cause the all the data to be discarded or flushed from the
RX FIFO. Packet discards are described in more detail in
the Packet Discard section.
COLLISION
General
Collisions occur when transmission and reception occur at
the same time on the physical media. Collisions on the
physical media are detected by an external Physical Layer
device and indicated to the 84302 by the assertion of the
COL pin on the PHY interface for that port. A collision
causes the transmission of a packet to be halted and
automatically retransmitted at a ater ime, according o he
backoff algorithm.
Collisions only apply to Half Duplex mode; the collision
function is disabled and COL pin ignored in Full Duplex
mode.
Backoff and Retransmission
When a collision is signalled to the device from the PHY
during the first 512 bits of a transmit packet, the backoff
algorithm halts transmission for a predetermined amount
of time, per IEEE 802.3 specification. This predetermined
interval is referred to as the backoff interval. The backoff
interval s a random number that s an exponential function
of the number of times a collision has occurred while
attempting to transmit a particular packet. After the
backoff internal has expired, the packet is automatically
retransmitted.
The random number generator used by the backoff algo-
rithm can be reset separately for each port by setting the
backoff counter reset bit in the Configuration 3 register.
Per IEEE 802.3 specifications, if a particular packet has
been halted 16 times because of collisions and another
collision occurs, then the packet transmission will be
permantly halted and that transmit packet will be dis-
carded. Refer to the Packet Discard section for more
details on packet discards.
The 16 retries and automatic retransmission of a packet
after a collision can be turned off by asserting the
ONETRYMODE pin. When this pin is pinstrapped active
high, the transmit packet will be discarded if the transmis-
sion is unsuccessful due to a single collision, i.e. no
transmission retry is attempted after a collision.
Late Collision
When a collision is signalled to the device from the PHY
after the first 512 bits of a transmit packet, the collision is
determined to be a late collision. Late collision, per IEEE
802.3 specifications, are considered errors. Upon the
detection of a ate collision, the transmit packet affected by
the ate collision s discarded. Refer to the Packet Discard
section for more details on packet discards.
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