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參數(shù)資料
| 型號： | 84302 |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器) |
| 中文描述： | 4端口快速以太網(wǎng)控制器（4端口快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 16/96頁 |
| 文件大?。?/td> | 826K |
| 代理商： | 84302 |
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84302 4-Port
Fast Ethernet Controller
4-16
MD400171/C
TXRET_[1:4] is a transmit packet discard output, one per
port. TXRET_[1:4] s asserted when an error was detected
on a transmit packet. When a transmit error s detected on
a packet, the remaining contents of the packet is flushed
from the TX FIFO and TXRET_[1:4] is latched active high
to indicate that the error occurred. TXRET_[1:4] for the
selected port can be cleared by asserting the clearing
signal, CLRTXERR. While TXRET_[1:4] is latched high,
the TX FIFO input is blocked and no data can be loaded
into it until it is cleared with CLRTXERR. See the Packet
Discard section for more details on discards and
TXRET_[1:4].
TXNOCRC is an input which can disable the internal
generation and appending of the 4 byte CRC value onto
the end of the data packet. TXNOCRC is sampled on
rising edges of SCLK and can be asserted on any SCLK
cycle between the first and last double word of a packet to
cause the removal or addition of the CRC to that packet.
CRC generation can also be disabled by setting the
transmit CRC disable bit in the Configuration 1 register.
The interaction between the TXNOCRC pin and CRC
disable bit is defined in Table 3.
FCNTRL_[1:4] is an input, one per port, which will cause
the automatic generation and transmission of a MAC
Control Pause frame n Full Duplex mode and JAM packet
in Half Duplex mode. FCNTRL_[1:4] is input on rising
edges of SCLK. See the Flow Control, Auotmatic JAM,
and MAC Control Frame sections for more details about
these features.
Receive Read Operation
All receive and transmit data is clocked in/out on rising
edges of the system clock, SCLK. The SCLK input needs
Table 2. Byte Enable Pin vs. Valid Byte Position
RXTXBE[3:0] Pins
Valid Byte Position on
RXTXDATA[31:0]
RXTXBE3
RXTXDATA[31:24]
RXTXBE2
RXTXDATA[23:16]
RXTXBE1
RXTXDATA[15:8]
RXTXBE0
RXTXDATA[7:0]
The end of frame I/O pin, RXTXEOF, ndicates which data
word is the last word of the Ethernet data packet.
RXTXEOF is configured to be an input during a write
operation. RXTXEOF is input on the same SCLK rising
edge as the first and last word of the data packet.
There are four transmit FIFO ready outputs, one per port,
on he TXRDY_[1:4] pins. The ransmit FIFO ready output
is a transmit FIFO watermark signal which indicates when
the transmit FIFO space has exceeded the programmable
transmit FIFO threshold value. TXRDY_[1:4] will be
asserted or deasserted by the device on rising edges of
SCLK, depending on the fullness of the transmit FIFO.
Refer to the transmit FIFO section for more details on
TXRDY_[1:4].
In addition to the TXRDY output, there is also a FIFO
space/data available output indication on the SPDTAVL
pin. During a write operation, the SPDTAVL output is a
space available (almost full) indication for the transmit
FIFO and it is asserted active high if there is more than 2
double words of space available in the transmit FIFO.
Figure 5. Little Endian vs. Big Endian Format
BIG ENDIAN
LITTLE
ENDIAN
(DEFAULT)
PREAMBLE
DA0
DA16
DA8
DA7
DA15
DA23
RXTXDATA0 . . . . . . .RXTXDATA7
RXTXDATA8 . . . . . . .RXTXDATA15
RXTXDATA16 . . . . . .RXTXDATA23
. . . . . . . . . . . . .
. . . . . . . . . . . . .
. . . . . . . . . . . . .
RXTXDATA24 . . . . . .RXTXDATA31
RXTXDATA16 . . . . . .RXTXDATA23
RXTXDATA8 . . . . . . .RXTXDATA15
A
RXTXDATA24 . . . . . .RXTXDATA31
. . . . . . .
RXTXDATA0 . . . . . . .RXTXDATA7
RXTXDATA8
RXTXDATA15
. . . . . . .
RXTXDATA16 . . . . . . .
DA32
DA24
SOURCE ADDRESS
DA40
DA31
DA39
DA47
. . . . . . . . . . . . .
. . . . . . . . . . . . .
. . . . . . . . . . . . .
RXTXDATA0 . . . . . . .RXTXDATA7
RXTXDATA24 . . . . . .RXTXDATA31
RXTXDATA16
RXTXDATA23
. . . . . . .
RXTXDATA15 . . . . . . .
A
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