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參數(shù)資料
| 型號(hào)： | 84302 |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器) |
| 中文描述： | 4端口快速以太網(wǎng)控制器（4端口快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 30/96頁 |
| 文件大?。?/td> | 826K |
| 代理商： | 84302 |
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84302 4-Port
Fast Ethernet Controller
4-30
MD400171/C
COUNTERS
General
The 84302 has a set of 51 counters per port. These
counters provide the necessary statistics to completely
support the following specifications:
(1) RMON Statistics Group (IETF RFC 1757)
(2) SNMP Interfaces Group (IETF RFC 1213 & 1573)
(3) Ethernet-Like MIB (IETF RFC 1643)
(4) Ethernet MIB (IEEE 802.3u Clause 30)
The counter set ncludes the packet and octet statistics for
transmit side. The RMON specs literally state that packet
and octet counters should only tabulate received informa-
tion. This s sometimes nterpreted to mean both transmit-
ted and received information because Ethernet was origi-
nally a shared media protocol. As such, transmit packet
and octet counters are also available in counters #17-26
and can be summed with the receive packet and octet
counts if desired.
Table 10. Reset Description
Name
Initiated By
Reset Action
Device
Reset
RESET Pin
Asserted Low
Reset Datapath
Flush Transmit FIFO
Flush Receive FIFO
Reset Bits to Defaults
Reset Counters to 0
Datapath
Reset
Data Path Reset
Bit in
Configuration 4
Register
Reset Datapath
Flush Transmit FIFO
Flush Receive FIFO
Counter
Reset
Counter Reset Bit
in Configuration
4 Register
Reset Counters to 0
The device can be programmed to eliminate the last
autogenerated Pause frame with pause_time=0 by clear-
ing low the MAC Control frame end pause bit in the
Configuration 4 register.
The structure of the autogenerated Pause frame is de-
scribed in Figure 7. Note that the source address and
pause_time parameter fields are programmable through
internal registers as shown in Figure 7.
Transmitter Pause Disable
Receive MAC Control rames normally pause he ransmit-
ter. Receive MAC Control frames can be programmed to
not pause the transmitter by clearing the MAC Control
frame enable bit n he Configuration 4 Register. When his
bit cleared low, received Pause frames do not affect the
transmitter.
Passthrough to FIFO
Receive MAC Control frames are normally discarded and
not passed to the receive FIFO. Receive MAC Control
frames can be passed o he receive FIFO by appropriately
setting the MAC Control frame passthrough bits in the
Configuration 4 register. These bits allow either all MAC
Control frames or just non-Pause frames to be passed to
the receive FIFO.
Reserved Multicast Address Disable
Receive MAC Control frames are normally rejected as
invalid if they do not have the reserved multicast address
in the destination address field. Receive MAC Control
frames can be accepted without regard to the contents of
the destination address field by appropriately setting the
MAC Control frame address filter bit n the Configuration 4
register. When this bit is cleared low, any value in the
destination address field will be accepted as a valid ad-
dress.
RESET
The device has hree resets. All hree resets are described
in Table 10.
From Table 10, note that the device reset is controlled by
a pin, and it must be asserted at powerup in order to
properly initialize the device. When this device reset is
initiated, it forces the other two reset bits to their default
states of logic 1; these two reset bits must then be cleared
to logic 0 for normal device operation to begin.
The RESET pin or bit should be asserted for a minimum of
10
μ
s. During the RESET period, the TXC and RXC input
clocks from the external PHY must be active. After the
RESET pin or bit has been deaaserted, the device should
be ready for normal operation after 40 SCLK cycles.
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