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參數(shù)資料
| 型號： | 84302 |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器) |
| 中文描述： | 4端口快速以太網(wǎng)控制器（4端口快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 22/96頁 |
| 文件大小： | 826K |
| 代理商： | 84302 |
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84302 4-Port
Fast Ethernet Controller
4-22
MD400171/C
TRANSMIT FIFO
General
The transmit FIFO acts as a temporary buffer between the
System Interface and transmit MAC section. The transmit
FIFO size is 128 bytes. Data is clocked into the transmit
FIFO with the System Interface clock, SCLK. Data is
automatically clocked out of the transmit FIFO with the
PHY Interface TXC clock whenever (1) a full packet is
loaded into the FIFO (evidenced by an EOF being written
into he FIFO on he System nterface), or (2) he FIFO data
exceeds the Transmit Control threshold setting. There is
one programmable watermark output and one almost
empty output which aid in managing the data flow into the
transmit FIFO.
Transmit Control Threshold
The Transmit Control feature causes a packet in the
transmit FIFO to be automatically transmitted once the
transmit FIFO data exceeds the Transmit Control threhold
or a full packet has been oaded nto the transmit FIFO (an
EOF write occurred for that packet).
that it does not contain new data since the last read. After
the RX Status register has been read, that register is
available to be written with new status information.
The bits n he RX Status register are a combination of error
detect and packet status bits. Bit 5 in the RX Status
register indicates if the receive packet had an error, i.e. is
it good or not. If the receive packet had an error, the error
is reported in Bits 0-4 (FIFO overflow, CRC error, under-
size packet, oversize packet, and dribble error). Bit 6
indicates that the first 12 bytes of the packet have been
successfully received (the first 12 bytes contain the packet
header). Bit 7 in the RX status register indicates whether
the register contain information on a new packet. All the
bits in the RX Status register are latched high, stay high
until they are read, and cleared low when read.
All he bits n he RX Status register assert nterrupt with he
exception of the dribble error detect (Bit 2) and RX update
(Bit 7) bits. An interrupt caused by the good packet bit (Bit
5) and the receive first 12-Bytes bit (Bit 6) will normally be
disabled but can be enabled by setting the appropriate
interrupt enable bits in the RX Command register. Inter-
rupts caused by all the receive bits can also be disabled by
setting the receive nterrupt disable bit n the Configuration
1 register. A summary of all the bits that assert interrupt
and their associated enable/disable bits is described in
Table 13.
MAC Control Frame Check
The length/type field is checked to detect whether the
packet is a valid MAC Control frame. Refer to the MAC
Control Frame section for more details on MAC Control
frames.
The Transmit Control threshold is programmable over the
entire 128 byte ransmit FIFO range. The Transmit Control
threshold can be programmed with the four Transmit
Control threshold setting bits that reside in the Transmit
Control/Product ID register. Once the data in the FIFO
exceeds this threshold, then the packet is automatically
transmitted to the MAC and over the PHY Interface.
Watermark
There is one watermark for the transmit FIFO. This
watermark s output on the TXRDY pin. This watermark s
asserted when he ransmit FIFO space exceeds or equals
the programmable threshold associated with the water-
mark.
The transmit watermark threshold for TXRDY can be
programmed over the entire 128 byte TX FIFO range. The
watermark threshold can be programmed with four bits
that reside n he FIFO Threshold register. Once he space
in the FIFO exceeds or equals the threshold of the water-
mark, then the watermark output pin TXRDY is asserted
active low. The watermark stays asserted until the space
in the FIFO goes below the threshold.
Normally, the TXRDY watermark is asserted/deasserted
when the FIFO space goes below/above the TX FIFO
threshold, respectively. TXRDY can be configured to
deassert when either the threshold limit is exceeded or an
EOF is written to the TX FIFO by setting the TXRDY
function select bit in the Configuration 2 register. When
this bit is set, TXRDY will remain deasserted until the
packet n he TX FIFO has been completely ransmitted out
of the TX FIFO.
Almost Full Indication
There s an almost full output ndication for the the transmit
FIFO on the SPDTAVL pin. When a TX FIFO write
operation is in progress, the SPDTAVL ouput pin will be
asserted active low if there is less than 3 double words of
TX FIFO space available in the transmit FIFO.
TX Underflow
The transmit FIFO underflow condition occurs when the
TX FIFO is empty but the MAC still is requesting data to
complete he ransmission of a packet. If he ransmit FIFO
underflows, then (1) TXRET is asserted and latched, (2)
packet transmission to the MII is halted with TXEN being
deasserted, (3) all input data to the TX FIFO is blocked
until the TXRET signal is cleared with CLRERR. Refer to
the Packet Discard section for more information about
discards.
Discards
Certain error conditions detected for a given packet will
cause the data for that packet to be discarded or flushed
from the TX FIFO. Packet discards are described in more
detail in the Packet Discard section.
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