參數(shù)資料
型號(hào)： 84302
廠商： LSI Corporation
英文描述： 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器)
中文描述： 4端口快速以太網(wǎng)控制器（4端口快速以太網(wǎng)控制器）
文件頁(yè)數(shù)： 19/96頁(yè)
文件大?。?/td> 826K
代理商： 84302
84302 4-Port
Fast Ethernet Controller
4-19
MD400171/C
The defer time is split into two separate periods. The first
period is programmable using the bits in the Transmit
Defer register. The second period s fixed. The total defer
time, also referred to as minimum IPG is determined by
the following equations:
100 & 10 Mbps MII Mode:
= INT((INT(t
D
/40)+5+DEFER)2)+2
t
DEFER
10 Mbps Serial Mode:
= INT((INT(t
/100)+17+DEFER/8)+2
=
Defer Time in Bytes
INT(x)
=
Use Whole Number Portion of x
t
D
=
Delay from falling edge of TXEN to
falling edge of CRS (Half Duplex)
=
0 (Full Duplex)
DEFER
=
Decimal Value of Transmit Defer
Register Bits DEFER[7:0]
t
DEFER
The computed defer time (minimum IPG) values for each
setting of the transmit defer register bits are also shown in
Appendix A.
Transmit Control
Packet transmission by the MAC is initiated once the
packet data has exceeded the programmable Transmit
Control threshold or an entire packet has been loaded in
the transmit FIFO. This function is described in more
detail in the Transmit FIFO section.
AutoRetransmission Upon Collision
In Half Duplex mode, the device will automatically retrans-
mit a packet that has been interrupted due to a collision.
This is described in more detail in the Collision section.
TX Status
Each port contains two TX Status registers which store the
status of the last two packets transmitted. With each
transmission attempt, successful or not, one of the status
registers is written with the status for that packet. When a
TX Status register is written, the transmit status update bit
is set in that register to indicate that the register contains
new information. The data remains latched in the TX
Status registers until it is read out via the Register Inter-
face. When a TX Status register is read, the transmit
status update bit is cleared low to indicate that it does not
contain new data since the last read. After a TX Status
Resigter has been read, that register is available to be
written with new status information for another packet.
These two TX Status registers share the same register
address. If both registers contain new status information,
the first read to that register address will give the status of
the second to ast packet transmitted, and the second read
will give the status of the last packet transmitted.
There are three register bits which can modify the opera-
tion of the TX Transmit Status registers:
(1) The TX Status registers can be disabled, i.e.
status is never loaded into them, by setting the
transmit status disable bit inthe Configuration 2
register.
(2) The TX Status registers can be configured to
update continuously and not stay latched until
read by setting the transmit status register
update select bit in the Configuration 2 register.
(3) The TX Status registers can be configured to not
store status for packets affected by a collision by
setting the transmit status disable bit in the
Configuration 3 register.
The bits n he TX Status register are a combination of error
detect and packet status bits. Bit 3 n he TX Status register
indicates if the transmit packet had an error, i.e. was it
successfully transmitted or not. If the transmit packet was
not successfully transmitted due to error, the error is
reported n Bits 0, 2, 4, and 6 (FIFO underflow, 16 collision
error, carrier sense error, and late collision). Bit 1 is a
status bit and indicates if a collision occurred during the
transmission of the packet. Bit 5 indicates if the transmis-
sion of the packet was deferred waiting for the completion
of receiving a packet. Bit 7 in the TX status register
indicates whether the register has been updated for a new
packet since the last read. All the bits in the TX Status
register are atched high, stay high until they are read, and
cleared low when read.
All he bits n he TX Status register assert nterrupt with he
exception of the defer detect (Bit 5) bit and the TX Status
update bit (Bit 7). Interrupts caused by all of these bits will
normally be disabled but can be enabled by setting the
appropriate interrupt enable bits in the TX Command
register. A summary of all the bits that assert nterrupt and
their associated enable/disable bits is described in Table
13.
MAC Control Frame Generation
The transmit MAC can automatically generate and trans-
mit MAC Control Pause frames. MAC Control Pause
frames are used for flow control. This function s described
in more detail in the MAC Control Frame section.
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