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參數(shù)資料
| 型號(hào)： | 84302 |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器) |
| 中文描述： | 4端口快速以太網(wǎng)控制器（4端口快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 24/96頁 |
| 文件大?。?/td> | 826K |
| 代理商： | 84302 |
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84302 4-Port
Fast Ethernet Controller
4-24
MD400171/C
Collision Indication
There are status bits related to collisions in the TX Status
register indicating that (1) one or more collisions have
occurred while attempting transmission of a packet, (2) 16
or more collisions have occurred while attempting trans-
mission of a packet, and (3) a late collision has occurred
during packet transmission. These three bits will also
assert the interrupt pin for a given port.
PACKET DISCARD
General
The device can be programmed to discard receive and
transmit packets when certain error conditions are de-
tected. The detection of these error conditions can occur
in either the MAC or FIFO sections.
Transmit Discards
Transmit packets will be automatically discarded if certain
error conditions are detected. These error conditions are
described in Table 5. When a discard error is detected for
a transmit packet, (1) transmission is terminated for that
packet (i.e. TXEN is deasserted), (1) the packet is dis-
carded, that s, all data n the packet containing the error s
flushed from the transmit FIFO, and (3) TXRET s asserted
if the packet was being input from the System Interface
when the discard occurred.
Table 5. Transmit Discard Conditions
Discard Condition
Description
Transmit FIFO
Underflow
TX FIFO empty while
transmitting the packet.
TXEN is deasserted
Late Collision
A late collision occurred
while transmitting the
packet.
Carrier Sense Error
CRS never went active during
transmission or went from an
active to inactive state during
transmission.
16 Collisions
16 attempts to transmit the
packet all resulted in transmit
collision.
ONETRYMODE
and Collision
The ONETRYMODE pin is
high and a collisions occurs.
Receive Discards
Receive packets can be discarded if certain error condi-
tions are detected. These error conditions are described
in Table 6. When a discard condition is detected on a
receive packet, (1) all data is flushed from the receive
FIFO, (2) the input to the RX FIFO is blocked until the
beginning of the next packet and (3) the error condition is
indicated by the assertion of the RXDC pin. The packet
can then be discarded by asserting the RXABORT pin.
Each of the receive discard conditions can be individually
removed as a discard condition by appropriately setting
the discard bits n the RX Command register. When these
bits are set, a packet hat s afflicted with he error condition
indicated by that bit will not be discarded.
Table 6. Receive Discard Conditions
Discard Condition
Description
Receive FIFO
Overflow
Receive FIFO full.
CRC Error
Receive packet has CRC Error.
Oversize Packet
Receive packet is greater than
maximum packet size,
exclusive of
preamble & SFD. Maximum
packet size is programmable
between 1518-1533 bytes.
Undersize Packet
Receive packet is less than 64
bytes, exclusive of preamble &
SFD
RXABORT Pin
RXABORT pin was asserted
while the receive packet was
read out on the System
Interface.
Discard Output Indication
When a packet that is being receive/transmitted over the
System Interface has been automatically discarded, the
TXRET and RXDC output pins are asserted o ndicate hat
the discard happened. TXRET and RXDC are normally
latched high when a discard takes place. TXRET and
RXDC or he selected port can be cleared ow by asserting
the clearing pin, CLRTXERR and CLRRXERR, respec-
tively.
When TXRET and RXDC are asserted, all data is pre-
vented from being written to the transmit and receive
FIFO’s, respectively, as ong as the respective signals are
latched high. When these signals are cleared, then the
respective FIFO’s can be written to.
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